W3EG7217S-D3 Datasheet, PDF (6/12 Pages) White Electronic Designs Corporation – 128MB - 16Mx72 DDR SDRAM REGISTERED, ECC w/PLL

White Electronic Designs
W3EG7217S-D3
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM Component Only
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
dle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
Conditions
One device bank; Active = Precharge; tRC = tRC(MIN); tCK =
tCK(MIN); DQ,DM and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two
cycles.
One device bank; Active-Read-Precharge; Burst = 2; tRC =
tRC(MIN);tCK = tCK (MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
All device banks idle; Power- down mode; tCK = tCK(MIN);
CKE = (low)
CS# = High; All device banks idle; tCK = tCK(MIN); CKE =
high; Address and other control inputs changing once per
clock cycle. VIN = VREF for DQ, DQS and DM.
One device bank active; Power-down mode; tCK(MIN); CKE
= (low)
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle;
tCK = tCK(MIN); IOUT = 0mA.
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
tCK = tCK(MIN); DQ,DM and DQS inputs changing twice per
clock cycle.
tRC = tRC(MIN)
CKE ≤ 0.2V
Four bank interleaving Reads (BL = 4) with auto precharge
with tRC = tRC (MIN); tCK = tCK(MIN); Address and control
inputs change only during Active Read or Write commands.
DDR266@CL = 2
Max
900
1080
27
405
225
450
1170
1125
1980
27
2970
DDR266@CL = 2.5
Max
945
1080
27
360
180
405
1125
1080
1980
18
2925
DDR200@CL = 2
Max
945
1080
27
360
180
405
1125
1080
1980
18
2925
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
December 2004
Rev. 1
6
White Electronic Designs Corporation • [phone] • www.wedc.com