W3EG2128M64ETSR-JD3 Datasheet, PDF (6/13 Pages) White Electronic Designs Corporation – 2GB - 2x128Mx64 DDR SDRAM REGISTERED w/PLL

White Electronic Designs ^{W3EG2128M64ETSR-JD3}
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes PLL and register power
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
Conditions
One device bank; Active - Precharge; tRC=tRC
(MIN); tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and control
inputs changing once every two cycles.
One device bank; Active-Read-Precharge Burst
= 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA;
Address and control inputs changing once per
clock cycle.
All device banks idle; Power-down mode; tCK=tCK
(MIN); CKE=(low)
CS# = High; All device banks idle; tCK=tCK (MIN);
CKE = high; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ,
DQS and DM.
One device bank active; Power-Down mode; tCK
(MIN); CKE=(low)
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle.
Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; TCK= TCK (MIN); lOUT = 0mA.
Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK=tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle.
tRC = tRC (MIN)
CKE ≤ 0.2V
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN);
Address and control inputs change only during
Active Read or Write commands.
DDR333@
CL=2.5
Max
2720
3000
160
1350
560
1110
3200
3280
4140
475
5640
DDR266@
CL=2
Max
2720
3000
160
1350
560
1110
3200
3280
4140
475
5640
DDR266@
CL=2.5
Max
2520
2800
160
1270
480
1030
2960
3040
3980
475
5240
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
April 2005
Rev. 0
6
White Electronic Designs Corporation • [phone] • www.wedc.com