W3EG7266S-AD4 Datasheet, PDF (5/13 Pages) White Electronic Designs Corporation – 512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL

White Electronic Designs
W3EG7266S-AD4
-BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V (100, 133, 166MHz), VCC = VCCQ = +2.6V ± 0.1V (200MHz)
DDR400@
CL=3
DDR333@
CL=2.5
DDR266@
CL=2, 2.5
DDR200@
CL=2
Parameter
Symbol Conditions
Max
Max
Max
Max
Operating Current
IDD0 One device bank; Active - Precharge;
1670
1445
1445
1445
(MIN); DQ,DM and DQS inputs
changing once per clock cycle;
Address and control inputs changing
once every two cycles. TRC=TRC(MIN);
TCK=TCK
Operating Current
IDD1 One device bank; Active-
1940
1715
1715
1715
Read-Precharge; Burst = 2;
TRC=TRC(MIN);TCK=TCK (MIN); Iout
= 0mA; Address and control inputs
changing once per clock cycle.
Precharge Power-
IDD2P All device banks idle; Power-down
45
45
45
45
Down Standby
mode; TCK=TCK(MIN); CKE=(low)
Current
Idle Standby Current IDD2F CS# = High; All device banks idle;
770
680
680
680
TCK=TCK(MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ,
DQS and DM.
Active Power-Down IDD3P One device bank active; Power-down
405
315
315
315
Standby Current
mode; TCK(MIN); CKE=(low)
Active Standby
IDD3N CS# = High; CKE = High; One
815
725
725
725
Current
device bank; Active-Precharge;
TRC=TRAS(MAX); TCK=TCK(MIN); DQ,
DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per clock
cycle.
Operating Current
IDD4R Burst = 2; Reads; Continous burst;
1985
1760
1760
1760
One device bank active;Address
andcontrol inputs changing once
per clock cycle; TCK=TCK(MIN); IOUT
= 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continous burst;
2030
1850
1670
1670
One device bank active; Address and
control inputs changing once per clock
cycle; TCK=TCK(MIN); DQ,DM and
DQS inputs changing twice per clock
cycle.
Auto Refresh Current IDD5 TRC=TRC(MIN)
3360
2885
2885
2885
Self Refresh Current IDD6 CKE ≤ 0.2V
320
320
320
320
Operating Current
IDD7A Four bank interleaving Reads (BL=4)
4325
3875
3875
3875
with auto precharge with TRC=TRC
(MIN); TCK=TCK(MIN); Address and
control inputs change only during
Active Read or Write commands
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
October 2004
Rev. 7
5
White Electronic Designs Corporation • [phone] • www.wedc.com