W3EG72128S-D3 Datasheet, PDF (5/12 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx72 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG72128S-D3
-JD3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V; DDR400: VCC = VCCQ = 2.6V ± 0.1V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
Operating Current
IDD0 One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
Operating Current
IDD1 One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
Precharge Power-
IDD2P All device banks idle; Power-down
Down Standby Current
mode; tCK=tCK (MIN); CKE=(low)
Idle Standby Current
IDD2F CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-
Down mode; tCK (MIN); CKE=(low)
Active Standby Current IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
Auto Refresh Current IDD5 tRC = tRC (MIN)
Self Refresh Current
IDD6 CKE ≤ 0.2V
Operating Current
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
DDR400@
CL=3
Max
2475
2745
90
990
810
1080
2790
2835
4185
90
5130
DDR333@
CL=2.5
Max
2070
2340
90
810
630
900
2385
2475
3510
90
4545
DDR266@
CL=2
Max
2070
2340
90
810
630
900
2385
2475
3510
90
4500
DDR266@
CL=2.5
Max
2070
2340
90
810
630
900
2385
2475
3510
90
4500
DDR200@
CL=2
Max
Units
mA
2070
mA
2340
90
rnA
mA
810
630
mA
mA
900
mA
2385
rnA
2475
3510
mA
90
mA
mA
4500
May 2005
Rev. 3
5
White Electronic Designs Corporation • [phone] • www.wedc.com