W3EG6467S-D4 Datasheet, PDF (5/12 Pages) White Electronic Designs Corporation – 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG6467S-D4
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
Parameter
Symbol Conditions
DDR403
@CL=3
Max
DDR333
@CL=2.5
Max
DDR266
@CL=2, 2.5
Max
Operating Current
One device bank; Active - Precharge;
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and
IDD0 DQS inputs changing once per clock cycle;
Address and control inputs changing once
every two cycles.
1600
1440
Operating Current
One device bank; Active-Read-Precharge;
IDD1
Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout =
0mA; Address and control inputs changing
once per clock cycle.
1800
1640
Precharge Power-
Down Standby Current
Idle Standby Current
IDD2P
All device banks idle; Power- down mode;
tCK=tCK(MIN); CKE=(low)
CS# = High; All device banks idle;
IDD2F
tCK=tCK(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
48
48
400
320
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode;
tCK(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS(MAX);
Active Standby Current
IDD3N
tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle.
560
480
880
720
Operating Current
Operating Current
Burst = 2; Reads; Continous burst; One
IDD4R
device bank active;Address and control
inputs changing once per clock cycle;
tCK=tCK(MIN); Iout = 0mA.
Burst = 2; Writes; Continous burst; One
device bank active; Address and control
IDD4W inputs changing once per clock cycle;
tCK=tCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
2160
1840
2160
1800
Auto Refresh Current
Self Refresh Current
Operating Current
IDD5 tRC=tRC(MIN)
IDD6 CKE ≤ 0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
IDD7A tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write
commands.
2240
2000
48
48
3120
2960
DDR200
@CL=2
Max
1360
Units
mA
1560
mA
48
mA
320
mA
480
mA
720
mA
1840
mA
1800
mA
2000
mA
48
mA
2720
mA
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 1
5
White Electronic Designs Corporation • [phone] • www.wedc.com