W3EG6462S-D3 Datasheet, PDF (5/13 Pages) White Electronic Designs Corporation – 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG6462S-D3
-JD3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby
Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
Symbol
IDD0
IDD1
IDD2P
Conditions
One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
DDR400@
CL=3
Max
2200
2480
64
DDR333@
CL=2.5-3-3
Max
1960
2320
64
DDR266@
CL=2
Max
1800
2080
64
IDD2F CS# = High; All device banks idle;
960
800
720
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ,
DQS and DM.
IDD3P One device bank active; Power-Down
640
480
400
mode; tCK (MIN); CKE=(low)
IDD3N CS# = High; CKE = High; One device
1120
960
800
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
IDD4R Burst = 2; Reads; Continuous burst;
2720
2360
2000
One device bank active; Address and
control inputs changing once per clock
cycle; TCK= TCK (MIN); lOUT = 0mA.
IDD4W Burst = 2; Writes; Continuous burst;
2680
2360
2000
One device bank active; Address and
control inputs changing once per clock
cycle; tCK=tCK (MIN); DQ,DM and DQS
inputs changing once per clock cycle.
IDD5 tRC = tRC (MIN)
3200
3000
2680
IDD6 CKE ≤ 0.2V
64
64
64
IDD7A Four bank interleaving Reads (BL=4)
4880
4240
3600
with auto precharge with tRC=tRC (MIN);
tCK=tCK (MIN); Address and control
inputs change only during Active Read
or Write commands.
DDR266@
CL=2.5
Max
1800
2080
64
720
400
800
2000
2000
2680
64
3600
DDR200@
CL=2
Max
1800
2080
64
720
400
800
2000
2000
2680
64
3600
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
May 2005
Rev. 4
5
White Electronic Designs Corporation • [phone] • www.wedc.com