W3EG64255S-JD3 Datasheet, PDF (5/13 Pages) White Electronic Designs Corporation – 2GB - 2x128Mx64 DDR SDRAM REGISTERED, w/PLL

White Electronic Designs
W3EG64255S-JD3
ADVANCED
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
Rank 1
Symbol Conditions
IDD0 One device bank; Active - Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
IDD1 One device bank; Active-Read-
Precharge Burst = 2; tRC = tRC (MIN);
tCK = tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
IDD2P All device banks idle; Power-down
mode; tCK = tCK (MIN); CKE = (low)
IDD2F CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ,
DQS and DM.
IDD3P One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS
(MAX); tCK = tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
IDD4R Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK = tCK (MIN); lOUT = 0mA.
IDD4W Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ,DM and DQS
inputs changing once per clock cycle.
IDD5 tRC = tRC (MIN)
IDD6 CKE ≤ 0.2V
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control
inputs change only during Active Read
or Write commands.
DDR333@CL=2.5
Max
4140
4680
180
1620
1260
1800
4770
4590
7020
180
9090
DDR266:@CL=2, 2.5
Max
4140
4680
180
1620
1260
1800
4770
4590
7020
180
9000
DDR200@CL=2
Max
3690
4230
180
1440
1080
1620
4230
4050
6660
180
7920
Units
mA
Rank 2
Standby
State
IDD3N
mA
IDD3N
rnA
IDD2P
mA
IDD2F
mA
IDD3P
mA
IDD3N
mA
IDD3N
rnA
IDD3N
mA
IDD3N
mA
IDD6
mA
IDD3N
April 2005
Rev. 3
5
White Electronic Designs Corporation • [phone] • www.whiteedc.com