W3EG6418S-D3 Datasheet, PDF (5/12 Pages) White Electronic Designs Corporation – 128MB - 16Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG6418S-D3
-JD3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
DDR266@CL=2 DDR266@CL=2.5 DDR200@CL=2
Max
Max
Max
Operating
IDD0 One device bank; Active - Precharge; tRC=tRC (MIN);
Current
tCK=tCK (MIN); DQ,DM and DQS inputs changing once
per clock cycle; Address and control inputs changing
1000
880
880
once every two cycles.
Operating
IDD1 One device bank; Active-Read-Precharge Burst = 2;
Current
tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and
1080
960
960
control inputs changing once per clock cycle.
Precharge
IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN);
Power-
Down Standby
CKE=(low)
24
24
24
Current
Idle Standby
IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE =
Current
high; Address and other control inputs changing once per
360
360
360
clock cycle. VIN = VREF for DQ, DQS and DM.
Active Power-
IDD3P One device bank active; Power-Down mode; tCK (MIN);
Down Standby
CKE=(low)
200
200
200
Current
Active Standby
IDD3N CS# = High; CKE = High; One device bank; Active-
Current
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address and
400
400
400
other control inputs changing once per clock cycle.
Operating
IDD4R Burst = 2; Reads; Continuous burst; One device bank
Current
active; Address and control inputs changing once per
1120
1040
1040
clock cycle; TCK= TCK (MIN); lOUT = 0mA.
Operating
IDD4W Burst = 2; Writes; Continuous burst; One device bank
Current
active; Address and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs
1120
1000
1000
changing once per clock cycle.
Auto Refresh
Current
IDD5 tRC = tRC (MIN)
2120
1760
1760
Self Refresh
Current
IDD6 CKE ≤ 0.2V
24
24
24
Operating
IDD7A Four bank interleaving Reads (BL=4) with auto precharge
Current
with tRC=tRC (MIN); tCK=tCK (MIN); Address and control
inputs change only during Active Read or Write
2840
2640
2640
commands.
* Module IDD was calculated on the basis of component IDD and can be different measured according to DQ loading cap.
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
5
White Electronic Designs Corporation • [phone] • www.wedc.com