W3EG64128S-D3 Datasheet, PDF (5/12 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED

White Electronic Designs
W3EG64128S-D3
-JD3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
DDR400@
CL=3
Max
Operating Current
IDD0 One device bank; Active - Precharge; tRC=tRC (MIN);
2200
tCK=tCK (MIN); DQ,DM and DQS inputs changing
once per clock cycle; Address and control inputs
changing once every two cycles.
Operating Current
IDD1 One device bank; Active-Read-Precharge Burst = 2;
2520
tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per clock cycle.
Precharge Power-
IDD2P All device banks idle; Power-down mode; tCK=tCK
80
Down Standby Current
(MIN); CKE=(low)
Idle Standby Current
IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE 880
= high; Address and other control inputs changing
once per clock cycle. VIN = VREF for DQ, DQS and
DM.
Active Power-Down
IDD3P One device bank active; Power-Down mode; tCK
720
Standby Current
(MIN); CKE=(low)
Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-
960
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continuous burst; One device bank 2640
active; Address and control inputs changing once per
clock cycle; TCK= TCK (MIN); lOUT = 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continuous burst; One device bank 2680
active; Address and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
Auto Refresh Current
IDD5 tRC = tRC (MIN)
3720
Self Refresh Current
IDD6 CKE £ 0.2V
96
Operating Current
IDD7A Four bank interleaving Reads (BL=4) with auto
4800
precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address
and control inputs change only during Active Read or
Write commands.
DDR333@
CL=2.5
Max
1840
DDR266@
CL=2
Max
1840
2080
2080
80
80
720
720
560
560
800
800
2120
2120
2360
2080
3120
3120
80
80
4040
4000
DDR266@
CL=2
Max
1840
2080
80
720
560
800
2120
2080
3120
80
4000
DDR266@
CL=2.5
Max
1840
2080
80
720
560
800
2120
2080
3120
80
4000
DDR200@
CL=2
Max
1840
2080
80
720
560
800
2120
2080
3120
80
4000
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
May 2005
Rev. 5
5
White Electronic Designs Corporation • [phone] • www.wedc.com