W3EG64128S-AD4 Datasheet, PDF (5/9 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL

White Electronic Designs
W3EG64128S-AD4
-BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°c ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Parameter
Operating Current
Operating Current
Precharge Power-Down
Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
Symbol Conditions
One device bank; Active - Precharge;
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS
IDD0 inputs changing once per clock cycle; Address
and control inputs changing once every two
cycles.
One device bank; Active-Read-Precharge;
IDD1
Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout =
0mA; Address and control inputs changing
once per clock cycle.
IDD2P
All device banks idle; Power- down mode;
tCK=tCK(MIN); CKE=(low)
CS# = High; All device banks idle;
IDD2F
tCK=tCK(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
VIN = VREF for DQ, DQS and DM.
IDD3P
One device bank active; Power-down mode;
tCK(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS(MAX);
IDD3N
tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle.
Burst = 2; Reads; Continous burst; One
IDD4R
device bank active;Address and control inputs
changing once per clock cycle; tCK=tCK(MIN);
Iout = 0mA.
Burst = 2; Writes; Continous burst; One
device bank active; Address and control inputs
IDD4W changing once per clock cycle; tCK=tCK(MIN);
DQ,DM and DQS inputs changing twice per
clock cycle.
IDD5 tRC=tRC(MIN)
IDD6 CKE ≤ 0.2V
Four bank interleaving Reads (BL=4) with auto
IDD7A
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only
during Active Read or Write commands.
DDR333@CL=2.5
Max
2915
3315
96
1075
800
1795
3795
4275
5235
355
7955
DDR266@CL=2.5
Max
2915
3315
96
1075
800
1795
3795
4275
5235
355
7955
DDR200@CL=2
Max
2915
3315
96
1075
800
1795
3795
4275
5235
355
7955
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
May 2004
Rev. 0
5
White Electronic Designs Corporation • [phone] • www.wedc.com