W3EG264M64EFSU-D4 Datasheet, PDF (5/11 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx64 DDR SDRAM, UNBUFFERED, FBGA

White Electronic Designs ^{W3EG264M64EFSU-D4}
ADVANCED
IDD SPECIFICATIONS AND CONDITIONS
0°C ≤ TA ≤ +70°C; VCC, VCCQ = +2.5V ±0.2V
DDR400: VCC = VCCQ = +2.6V ±0.2V
MAX
PARAMETER/CONDITION
SYM DDR400 DDR333 DDR266 DDR266 UNITS
@CL=3 @CL=2.5 @CL=2 @CL=2.5
OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK
(MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs
changing once every two clock cycles
IDD0 2475 2070 2070 1845 mA
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC
(MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock
cycle
IDD1 2745 2340 2340 2115 mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
IDD2P
90
90
90
90
mA
mode; tCK = tCK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = IDD2F 990
810
810
720
mA
HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ,
DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down
mode; tCK = tCK (MIN); CKE = LOW
IDD3P
810
630
630
540
mA
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC =
IDD3N 1080
900
900
810
mA
tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
IDD4R 2790 2385 2385 2115
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active;
IDD4W 2790 2295 2295 2025 mA
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle
AUTO REFRESH BURST CURRENT:
tREFC = tRFC (MIN)
IDD5 4185 3510 3510 3330 mA
SELF REFRESH CURRENT: CKE ≤ 0.2V
IDD6
90
90
90
90
mA
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto
precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change
only during Active READ, or WRITE commands
IDD7 5130 4545 4545 3960 mA
August 2005
Rev. 0
5
White Electronic Designs Corporation • [phone] • www.wedc.com