W3DG64128V-D1 Datasheet, PDF (5/7 Pages) White Electronic Designs Corporation – 1GB - 2x64Mx64 SDRAM, UNBUFFERED w/PLL

White Electronic Designs
W3DG64128V-D1
PRELIMINARY
AC TIMING PARAMETERS
Speed Grade
100MHz
Symbol
tCK
tCH
tCL
tIS
Parameter
Clock Period
Clock High Time Rated @1.5V
Clock Low Time
Input Setup Times
Min
Max
10
3
3
Address/ Command & CKE
2
Data
2
tIH
tAC
tOH
tOHZ
tCCD
tCBD
tCKE
tRP
tRAS
tRCD
tRRD
tRC
tDQD
tDWD
tMRD
tROH
tDQZ
tDQM
tDPL
tDAL
tSB
tSRX
tPDE
tCKSTP
tREF
tRFC
Input Hold Times
Address/Command & CKE
Data
Output Valid From Clock
CAS# Latency = 2 or 3,
LVTTL levels, Rated @ 50
pF all outputs switching
Output Hold From Clock Rated @ 50 pF (1.8 ns @ 0 pf)
Output Valid to Z
CAS to CAS Delay
CAS Bank Delay
CKE to Clock Disable
RAS Precharge Time
RAS Active Time
Activate to Command Delay (RAS to CAS Delay)
RAS to RAS Bank Activate Delay
RAS Cycle Time
DQM to Input Data Delay
Write Cmd. to Input Data Delay
Mode Register set to Active delay
Precharge to O/P in High Z
DQM to Data in High Z for read
DQM to Data mask for write
Data-in to PRE Command Period
Data-in to ACT (PRE) Command period (Auto precharge)
Power Down Mode Entry
Self Refresh Exit Time
Power Down Exit Set up Time
Clock Stop During Self Refresh or Power Down
Refresh Period
Row Refresh Cycle Time
1
1
6.0
(tco = 5.2)
3
3
9
1
1
1
20
50
20
20
70
0
0
3
CL
2
0
20
5
1
10
1
200
64
80.0
1. Access times to be measured w/input signals of 1 V/ns edge rate, 0.8 V to 2.0 V, tCO is clock to output with no load.
2. CL = CAS Latency
3. Data Masked on the same clock
4. Self refresh Exit is asynchronous, requiring 10 ns to ensure initiation. Self refresh exit is complete in 10 ns + tRC.
5. Timing is asynchronous. If tIS is not met by rising edge of CK then CKE is assumed latched on next cycle.
6. If the clock is stopped during self refresh or power down, 200 clocks are required before CKE is high.
Speed Grade
133MHz
Min
Max
7.5
2.5
2.5
1.5
1.5
0.8
0.8
5.4
(tco = 4.6)
Units
ns
ns
ns
ns
ns
ns
ns
ns
2.7
ns
2.7
7
ns
1
tCK
1
tCK
1
tCK
20
ns
45
ns
20
ns
15
ns
67.5
ns
0
tCK
0
tCK
3
tCK
CL
tCK
2
tCK
0
tCK
15
ns
5
tCK
1
tCK
10
ns
1
tCK
200
tCK
64
ms
75.0
ns
Notes
1
2
3
4
5
6
May 2005
Rev. 2
5
White Electronic Designs Corporation • [phone] • www.wedc.com