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W3H32M64E-XSBX Datasheet, PDF (1/6 Pages) White Electronic Designs Corporation – 32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package
White Electronic Designs
W3H32M64E-XSBX
ADVANCED*
32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package
FEATURES
Data rate = 667*, 533, 400
Write latency = Read latency - 1* tCK
Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 20mm
• 1.0mm pitch
DDR2 Data Rate = 667*, 533, 400
Supply Voltage = 1.8V ± 0.1V
Differential data strobe (DQS, DQS#) per byte
Commercial, Industrial and Military Temperature
Ranges
Organized as 32M x 64, user configurable as 2 x
32M x 32
Weight: W3H32M64E-XSBX - 2.5 grams typical
BENEFITS
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
Programmable CAS latency: 3, 4 or 5
62% SPACE SAVINGS vs. FPBGA
Reduced part count
42% I/O reduction vs FPBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradeable to 64M x 64 density (contact factory
for information)
* This product is under development, is not qualified or characterized and is subject
to change or cancellation without notice.
Posted CAS additive latency: 0, 1, 2, 3 or 4
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
11.0
11.0
11.0
11.0
90
19.0 FBGA
90
FBGA
90
FBGA
90
FBGA
Actual Size
W3H32M64E-XSBX
S
A
V
I
20
N
G
16
S
Area
I/O
Count
4 x 209mm2 = 836mm2
4 x 90 balls = 360 balls
320mm2
208 Balls
62%
42%
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com