EDI88512CA Datasheet, PDF (1/9 Pages) White Electronic Designs Corporation – 512Kx8 Monolithic SRAM, SMD 5962-95600

White Electronic Designs
EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
Access Times of 15, 17, 20, 25, 35, 45, 55ns
Data Retention Function (LPA version)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 512Kx8
Commercial, Industrial and Military Temperature Ranges
32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic Sidebrazed 400 mil DIP (Package 326)
• Ceramic 32 pin Flatpack (Package 344)
• Ceramic Thin Flatpack (Package 321)
• Ceramic SOJ (Package 140)
36 lead JEDEC Approved Revolutionary Pinout
• Ceramic Flatpack (Package 316)
• Ceramic SOJ (Package 327)
• Ceramic LCC (Package 502)
Single +5V (±10%) Supply Operation
The EDI88512CA is a 4 megabit Monolithic CMOS
Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary
standard for the four megabit device. All 32 pin packages
are pin for pin upgrades for the single chip enable 128K
x 8, the EDI88128CS. Pins 1 and 30 become the higher
order addresses.
The 36 pin revolutionary pinout also adheres to the
JEDEC standard for the four megabit device. The center
pin power and ground pins help to reduce noise in high
performance systems. The 36 pin pinout also allows the
user an upgrade path to the future 2Mx8.
A Low Power version with Data Retention (EDI88512LPA)
is also available for battery backed applications. Military
product is available compliant to Appendix A of MIL-
PRF-38535.
*This product is subject to change without notice.
FIG. 1 PIN CONFIGURATION
36 PIN
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
CS# 6
I/O0 7
I/O1 ⁸
Vcc ⁹
Vss 10
I/O2 ¹¹
I/O3 12
WE# 13
A5 14
A6 15
A7 16
A8 17
A9 18
36 pin
Revolutionary
36 NC
35 A18
34 A17
33 A16
32 A15
31 OE#
30 I/O7
29 I/O6
28 Vss
27 Vcc
26 I/O5
25 I/O4
24 A14
23 A13
22 A12
21 A11
20 A10
19 NC
32 PIN
TOP VIEW
A18 1
32 Vcc
A16 2
31 A15
A14 3
30 A17
A12 4
29 WE#
A7 5
28 A13
A6 6
27 A8
A5 7
32 pin
26 A9
A4 8
A3 9
Evolutionary
25 A11
24 OE#
A2 10
23 A10
A1 11
22 CS#
A0 12
21 I/O7
I/O0 13
20 I/O6
I/O1 14
19 I/O5
I/O2 15
18 I/O4
Vss 16
17 I/O3
A0-18
PIN DESCRIPTION
I/O0-7 Data Inputs/Outputs
A0-18 Address Inputs
WE# Write Enables
CS# Chip Selects
OE# Output Enable
VCC
Power (+5V ±10%)
VSS
Ground
NC
Not Connected
BLOCK DIAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
I/O0-7
WE#
CS#
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October 2004
Rev. 11
1
White Electronic Designs Corporation • [phone] • www.wedc.com