EDI88130CS Datasheet, PDF (1/9 Pages) White Electronic Designs Corporation – 128Kx8 Monolithic SRAM, SMD 5962-89598

White Electronic Designs
EDI88130CS
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
Access Times of 15*, 17, 20, 25, 35, 45, 55ns
Battery Back-up Operation
• 2V Data Retention (EDI88130LPS)
Single +5V (±10%) Supply OperationThe
EDI88130CS is a high speed, high performance,
128Kx8 bits monolithic Static RAM.
CS1#, CS2 & OE# Functions for Bus Control
Inputs and Outputs Directly TTL Compatible
Organized as 128Kx8
Commercial, Industrial and Military Temperature
Ranges
Thru-hole and Surface Mount Packages JEDEC
Pinout
• 32 pin Sidebrazed Ceramic DIP, 400 mil
(Package 102)
• 32 pin Sidebrazed Ceramic DIP, 600 mil
(Package 9)
• 32 lead Ceramic SOJ (Package 140)
• 32 pad Ceramic Quad LCC (Package 12)
• 32 pad Ceramic LCC (Package 141)
• 32 lead Ceramic Flatpack (Package 142)
An additional chip enable line provides system memory
security during power down in non-battery backed up
systems and memory banking in high speed battery
backed systems where large multiple pages of memory
are required.
The EDI88130CS has eight bi-directional input-output lines
to provide simultaneous access to all bits in a word.
A low power version, EDI88130LPS, offers a 2V data
retention function for battery back-up applications.
Military product is available compliant to MIL-PRF-
38535.
* 15ns access time is advanced information, contact factory for availability.
32 DIP
32 SOJ
32 CLCC
32 FLATPACK
TOP VIEW
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
VSS 16
32 VCC
31 A15
30 CS2#
29 WE#
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS1#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
FIGURE 1 – PIN CONFIGURATION
32 QUAD LCC
TOP VIEW
4 3 2 1 32 31 30
A7 5
29 _WE#
A6 6
28 _A13
A5 ⁷
27 _A8
A4 ⁸
26 _A9
A3 ⁹
25 _A11
A2 ¹⁰
24 _OE#
A1 ¹¹
23 _A10
A0 ¹²
22 _CS1#
I/O0 ¹³
21 _I/O7
14 15 16 17 18 19 20
PIN DESCRIPTION
I/O0-7
A0-16
WE#
CS1#, CS2
OE#
VCC
VSS
NC
Data Input/Output
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Not Connected
Block Diagram
Memory Array
A0-16
Address
Buffer
Address
Decoder
I/O
Circuits
I/O0-7
WE#
CS1#
CS2
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
Rev. 11
1
White Electronic Designs Corporation • [phone] • www.wedc.com