EDI2DL32256V Datasheet, PDF (1/8 Pages) White Electronic Designs Corporation – 256Kx32 Synchronous Pipline Burst SRAM 3.3V

EDI2DL32256V
256Kx32 Synchronous Pipline Burst SRAM 3.3V
FEATURES
s tKHQV times of 3.5, 3.8 and 4.0ns
s 166, 150 and 133 MHz clock speed
s DSP Memory Solution
• Texas Instruments’ TMS320C6201
• Texas Instruments’ TMS320C67x
s Package:
• 119 pin BGA, JEDEC MO-163
s 3.3V Operating Supply Voltage
s 3.5ns Output Enable access time
s Single Write Control and Output Enable Lines
s Single Chip Enable Line
s 56% space savings vs. monolithic TQFPs
s Multiple VCC and VSS pins
s Reduced inductance and capacitance
DESCRIPTION
The EDI2DL32256VxxBC is a 3.3V, 256Kx32 Synchronous Pipeline
Burst SRAM constructed with two 256Kx16 die mounted on a
multi-layer laminate substrate. The device is packaged in a 119
lead, 14mm by 22mm, BGA. It is available with clock speeds of166,
150 and 133 MHz. The device is a Pipeline Burst SRAM, allowing
the user to develop a fast external memory for Texas Instruments’
“C6x”. In Burst Mode data from the first memory location is
available in three clock cycles, while the subsequent data is
available in one clock cycle (3/1/1/1). Subsequent burst ad-
dresses are generated by the TMS320C6x DSP. Individual address
locations can also be read, allowing one memory access in 3 clock
cycles. All synchronous inputs are gated by registers controlled by
a positive-edge-triggered clock input (CLK). The synchronous in-
puts include all addresses, all data inputs, chip enable (CE\), burst
control input (ADSC\), byte write enables (BW0\ to BW3\) and
Write Enable (BWE\).
Asynchronous inputs include the output enable (OE\), burst mode
control (MODE), and sleep mode control (ZZ). The data outputs
(DQ), enabled by OE\, are also asynchronous.
Address lines and the chip enable are registered with the address
status controller (ADSC\) input pin.
FIG. 1
1
A VDD
B NC
C NC
D DQ16
E DQ18
F VDD
G DQ21
H DQ23
J VDD
K DQ31
L DQ29
M VDD
N DQ26
P DQ24
R NC
T NC
U VDD
1
PIN CONFIGURATION
2
3
4
5
6
7
A
A
NC
A
A
VDD A
NC
A ADSC\ A
A
NC B
A
A
VDD
A
A
NC C
NC
VSS
NC
VSS
NC DQ8 D
DQ17 VSS
CE\
VSS
DQ9 DQ10 E
DQ19 VSS
OE\
VSS
DQ11 VDD F
DQ20 BE2\ NC BE1\ DQ12 DQ13 G
DQ22 VSS
NC
VSS
DQ14 DQ15 H
VDD
NC
VDD
NC
VDD VDD J
DQ30 VSS CLK VSS
DQ6 DQ7 K
DQ28 BE3\ NC BE0\ DQ4 DQ5 L
DQ27 VSS BWE\ VSS
DQ3 VDD M
DQ25 VSS
A1
VSS
DQ1 DQ2 N
NC
VSS
A0
VSS
NC DQ0 P
A MODE VDD NC
A
NC R
NC
A
A
A
NC ZZ T
NC NC NC NC
NC VDD U
2
3
4
5
6
7
November 2000, Rev. 1
1
ECO #13417
A0-17
CLK
ADSC\
OE\
BWE\
CE\
MODE
ZZ
BE0\
BE1\
BE2\
BE3\
BLOCK DIAGRAM
256K X 16
SSRAM
256K X 16
SSRAM
DQ0-7
DQ8-15
DQ16-23
DQ24-31
White Electronic Designs Corporation • [phone] • www.whiteedc.com