P2V28S20DTP-7 Datasheet, PDF (19/51 Pages) Vanguard International Semiconductor – 128Mb SDRAM Specification

128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Multi Bank Interleaving READ (BL=4, CL=3)
CLK
Command
A0-9
ACT
Xa
tRCD
READ ACT
Y Xb
READ PRE
Y
A10
Xa
0 Xb
0
0
A11
Xa
Xb
BA0,1
00
00 10
10 00
DQ
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
/CAS latency
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CLK
Command
A0-9
A10
A11
BA0,1
DQ
ACT
Xa
tRCD
READ
Y
Xa
1
Xa
00
00
READ Auto-Precharge Timing (BL=4)
CLK
Command
AC T
READ
CL=3 DQ
CL=2 DQ
BL + tRP
BL
ACT
tRP
Xa
Xa
Xa
00
Qa0 Qa1 Qa2 Qa3
Internal precharge start
BL
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Internal Precharge Start Timing
JULY.2000
Page-18
Rev.2.2