VSC7128 Datasheet, PDF (7/10 Pages) Vitesse Semiconductor Corporation – Hex Port Bypass Circuit / Dual Repeater for 1.0625 Gb/s FC-AL Disk Arrays

VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7128
Hex Port Bypass Circuit / Dual Repeater
for 1.0625 Gb/s FC-AL Disk Arrays
Table 2: Pin Description
Pin #
16, 15
63, 62
20, 19
60, 59
26, 25
29, 28
38, 37
41, 40
51, 50
54, 53
23, 22
32, 31
35, 34
44, 43
47, 46
57, 56
24, 30
36, 42
49, 55
1, 13
2
3
4, 14
12
7,
10,
11
5, 17, 27,
48, 64
21, 33, 45, 58
8
6, 9, 18, 39,
52, 61
Name
IN1+, IN1-
IN2+, IN2-
OUT1+, OUT1-
OUT2+, OUT2-
LSI1+, LSI1-
LSI2+, LSI2-
LSI3+, LSI3-
LSI4+, LSI4-
LSI5+, LSI5-
LSI6+, LSI6-
LSO1+, LSO1-
LSO2+, LSO2-
LSO3+, LSO3-
LSO4+, LSO4-
LSO5+, LSO5-
LSO6+, LSO6-
SEL1, SEL2
SEL3, SEL4
SEL5, SEL6
SEL7, SEL8
REFCLK
RFSEL
FAIL1-
FAIL2-
FAILSEL
TEST1
TEST2
TEST3
VDD
VDD1, VDD2,
VDD3, VDD4
VDDA
VSS
Description
INPUT - Differential. Serial input to CRU1/CRU2 (AC Coupling recommended)
(Biased internally at V_DD/2).
OUTPUT - Differential. Serial output from MUX7/PBC6 (AC Coupling recommended).
INPUT - Differential. Serial input from disk drive ‘x’ to PBCx (AC Coupling
recommended) (Biased internally at V_DD/2).
OUTPUT - Differential. Serial output from PBCx to disk drive ‘x’ (AC Coupling
recommended).
INPUT - TTL. A LOW bypasses the disk drive input and passes the output from the
previous PBC to the output of PBCx. A HIGH selects the disk drive input (LSIx) as the
output of the PBC. SEL7 configures MUX7. SEL8 configures MUX8.
INPUT - TTL.. REFerence CLocK at 1/10th or 1/20th the baud rate (Nominally 53.125 or
106.25 MHz) as determined by RFSEL. Used for internal clock multiplier unit.
INPUT - TTL. ReFclk SELect. When HIGH, REFCLK is 1/10th the baud rate and would
normally be 106.25 MHz. When LOW, REFCLK is 1/20th the baud rate (53.125 MHz)
OUTPUT - TTL. When LOW, indicates that the output of CRU1/2 does not contain valid
Fibre Channel data.
INPUT - TTL. Selects the algorithm to drive the FAIL1-/FAIL2- outputs. When HIGH,
the “Multiple Frame Error Mode” is used. When LOW, the “Single Frame Error Mode” is
selected.
INPUT - TTL. LOW for factory test, HIGH for normal operation.
Power Supply. 3.3V Supply.
High-Speed Output Power Supply. 3.3V Supply for PECL drivers. VDD1 powers OUT1
and LSO1, VDD2 powers LSO2 and LSO3, VDD3 powers LSO4 and LSO5, VDD4
powers LSO6 and OUT2. If the pair of outputs are not used, VDDx may be grounded to
conserve power.
Analog Power Supply. 3.3V for Clock Multiplier PLL.
Ground.
G52177-0, Rev. 2.3
8/31/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
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