VSC7186 Datasheet, PDF (6/16 Pages) Vitesse Semiconductor Corporation – Quad Transceiver for Gigabit Ethernet

Quad Transceiver
for Gigabit Ethernet
RCi0
RCM=LOW
RCi1
RCi0
RCM=HIGH
RCi1
RXi(0:9)
SYNi
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7186
Figure 4: Receive Timing Waveforms
VALID
T₁
T₂
VALID
VALID
+/-SIi
RCi1
S0 S1 S2
R_LAT
Table 3: Receive AC Characteristics—
Parameters
Description
Min.
Max.
Units
Conditions
T₁
TTL Outputs Valid prior to
RCi1/RCi0 rise
3.0
—
ns.
T₂
TTL Outputs Valid after
RCi1 or RCi0 rise
2.0
—
ns.
T₃
Delay between rising edge of
RCi1 to rising edge of RCi0
10 x T_Ri
-500
10 x T_Ri
+500
ps.
T₄
Period of RCi1 and RCi0
1.98 x T_REF 2.02 x T_REF
ps.
T_R, T_F
TTL Output rise and fall
time
—
2.4
ns.
T_LOCK
Data acquisition lock time*
—
1400
bit
times
R_LAT
Latency from bit 0 of RXi0
appearing on SI to rising
edge of RCi1
12bc +
2.77ns
13bc +
7.28
Note:
* Note: Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3
@ 1.25Gb/s
@ 1.25Gb/s
T_Ri is the bit period of the
incoming data on Ri.
Whether or not locked to
serial data.
Between V_IL(max) and
V_IH(min), into 10 pf. load.
8b/10b IDLE pattern.
Tested on a sample basis
bc = bit clocks
ns = nanoseconds.
Page 6
 VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
G52306-0, Rev. 2.0
3/27/00