VSC6048 Datasheet, PDF (3/18 Pages) Vitesse Semiconductor Corporation – High-Speed Octal Programmable Timing Generator

Data Sheet
VSC6048
INxA
INxB
RCK
FSEL
BYP
VITESSE
SEMICONDUCTOR CORPORATION
High-Speed Octal
Programmable Timing Generator
Figure 1: Input Interleave
D SET Q
D _CLR Q
D SET Q
D _CLR Q
400MHz
D SET Q
D _CLR Q
TSET_CLK
DATA
PLL
800MHz
Figure 2: Functional Timing Diagram
TSET[0:9]
INA
INB
t_SETSU
IN_SU
OUT
TSET (0000000000)
OUT
TSET (1111111111)
RCK
t_RATETS
t_SETH
IN_H
t_PDTG(MIN)
t_OPW
t_PDV(SPAN)
t_PDTG(SPAN)
Time Set Input (TSET<0:9>)
This is a 10-bit TTL bus that controls the delay value of the vernier. The 3 MSBs control the 800MHz shift
register and the 7 LSBs control the fine delay element. The TSET data is clocked in by a pulse generated from
the input data. The setup time of the TSET data is the same as the input signals (INA, INB). The TSET data
must be stable by the time the input edge arrives at the input pin and data must then be held stable for at least
3.5ns after the input edge arrives at the pin.
G52335-0, Rev. 4.0
8/28/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
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