VSC7323 Datasheet, PDF (2/2 Pages) Vitesse Semiconductor Corporation – Meigs-IIe™ - 10 x 1G and 10G Ethernet MAC Chip

VSC7323
VSC7323 Meigs-IIe^™ - 10 x 1G and 10G Ethernet MAC Chip
GENERAL DESCRIPTION:
The VSC7323 (Meigs™-IIe) is a versatile
building block for a range of high-density
Gigabit Ethernet (GbE) and 10GbE
applications within the Enterprise, Metro,
and Core. The VSC7323 integrates 10
triple-speed MACs with integrated
SerDes, a single 10 Gigabit Ethernet (GbE) MAC with an
integrated 10 Gigabit Attachment Unit Interface (XAUI), an
OIF-compliant SPI-4.2 interface, a configurable parallel/serial
CPU interface, and dual MII Management interface.
Interfacing to the triple-speed MAC ports is accomplished
using MII for 10/100 Ethernet support and RGMII/GMII for GbE
support. The integrated GbE SerDes enables high density, cost-
efficient per port pricing for Ethernet aggregation services.
The full duplex, IEEE 802.3ae-compliant 10GbE MAC performs
pad insertion to ensure minimum frame length and CRC
generation as well as preamble, SFD, and IFG insertion on
transmit. On the receive side, the 10GbE MAC performs
Ethernet framing, CRC validation, and length monitoring.
The VSC7323 connects seamlessly to 10 Gb/s optical modules
such as XENPAK, X2, and XPAK using the integrated XAUI-
compliant serial interface. The quad lane 3.125 Gb/s interface
implements programmable pre-emphasis on transmit to
compensate for inter-symbol interference (ISI) and
equalization on receive to ensure reliability in high loss, high
distortion environments.
The internal ingress (Rx) and egress (Tx) FIFOs, which are
provisionable on a per port basis in increments of 2 kB, are
capable of handling short-haul flow control and
accommodating bursty traffic between the Ethernet MACs
and the SPI-4.2 system interface. The FIFO structures are
independently configurable for either cut-through or store-
and-forward modes.
The system side of the VSC7323, an industry standard OIF
SPI-4.2 interface, is used to seamlessly transfer packet date
between the VSC7323 and other devices such as network
processors, SONET/SDH mappers, and customer ASICs. The
16-bit SPI-4.2 interface can transmit (ingress) data at
312.5/390.625 MHz DDR and receive (egress) data in the range
of 311 to 450 MHz DDR.
The CPU interface can be configured as either a parallel
interface for seamless connection to PowerPC™ and Intel™
microprocessors or as a simple 4-line serial interface for
device initialization, control register, and per port statistic
access. The VSC7323 also integrates two MII Management
(MIIM) interfaces for managing and gathering status from the
PHY devices.
The VSC7323 is an ideal solution for OEMs designing 10 Gb/s
or higher solutions that require GbE and 10GbE support. The
VSC7323 also provides a seamless solution for frame-mapped
(GFP-F) Ethernet-over-SONET/SDH applications when used in
conjunction with Vitesse's VSC9118, a 10 Gb/s SONET/SDH VC
& GFP Mapper.
BLOCK DIAGRAM:
Quad Serial 3.125 GHz
XAUI Interface
10GbE MAC
VSC7323
Ingress (Rx)
FIFO
Tri-speed MAC
Ten Ports
10/100/1000 Mbps
Port #0
Port # 9
JTAG Port
Egress (Tx)
FIFO
Statistics
16-bit Parallel or 4-bit
Serial CPU Interface
For more information on Vitesse Products visit the Vitesse web site
at www.vitesse.com or contact Vitesse Sales at (800) VITESSE
or [e-mail]
©2003 Vitesse Semiconductor Corporation
741 Calle Plano
Camarillo, CA 93012, USA
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