VSC838 Datasheet, PDF (1/20 Pages) Vitesse Semiconductor Corporation – 3.2Gb/s 36x37 Crosspoint Switch

VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC838
3.2Gb/s
36x37 Crosspoint Switch
Features
• 36 Input by 37 Output Crosspoint Switch
• 3.2Gb/s NRZ Data Bandwidth
• Non-Blocking Architecture Broadcast and Multicast
Capabilities
• LVTTL/2.5V CMOS Control I/O (3.3V tolerant)
• Input Signal Activity Monitoring Function
• Integrated Signal Equalization (ISE) for Deterministic
Jitter Reduction
• 66MHz Dual Programming Port
• Parallel and Serial programming modes
• Programmable On-Chip I/O Termination
• Differential CML Output Drivers
• Single 2.5V Supply
• 6W Typical—Low Drive Mode
7W Typical—High Drive Mode
• High Performance 37.5mm, 480 TBGA Package
General Description
The VSC838 is a monolithic 36x36 asynchronous crosspoint switch, designed to carry broadband data
streams. The VSC838 also has an internal 37^th output channel which is used in conjunction with the Activity
Monitor to allow in system diagnostics.
A high degree of signal integrity is maintained throughout the chip via fully differential signal paths.
The crosspoint function is based on a multiplexer array architecture. Each data output is driven by a 36:1
multiplexer that can be programmed to one and only one of its 36 inputs. The signal path is unregistered and
fully asynchronous, so there are not any restrictions on the phase, frequency, or signal pattern at each input.
Each high-speed output is a fully differential, switched current driver with switchable on-die terminations
for maximum signal integrity. Data inputs are terminated on-die through 100Ω impedance between true and
complement inputs (see Input Termination section for further details).
A dual mode programming interface is provided that allows programming commands to be sent as serial
data or parallel data. Core programming can be random for each port address, or multiple program assignments
can be queued and issued simultaneously. The programming may be initialized to a “straight-through” configu-
ration (A0 to Y0, A1 to Y1, etc.) using the INIT pin.
Unused channels may be powered down to allow efficient use of the switch in applications that require only
a subset of the channels. Power-down can be accomplished in hardware, via dedicated power pins for pairs of
input and output channels, or in software by programming individual unused outputs with a disable code.
VSC838 Block Diagram
A0
2
2
Y0
A35 ²
µP
control
2
Y35
G52351-0, Rev 3.0
02/12/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
Internet: www.vitesse.com
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