VSC8184 Datasheet, PDF (1/2 Pages) Vitesse Semiconductor Corporation – 11.5-12.5Gb/s 1:16 Demultiplexer with Clock Recovery

11.5-12.5Gb/s 1:16 Demultiplexer with Clock Recovery
Physical
Layer
Products
VSC8184
Product Brief
Features:
• Continuous 11.5 to 12.5Gb/s
Lock-Range
• Low Power 1.6W (Typ)
• +3.3V Single Supply
• Single-End and Differential
Data Input
• 50 mV Input Sensitivity (Min)
• Slicing Threshold Voltage
Offset Control
• LVDS Outputs
• 180-195 or 719-781 MHz
Reference Clock
• Reliable 90-Ball BGA Package
• Up to 90°C Case Temperature
• On Chip Termination for all
LVDS Inputs
Specifications:
• 11.5 to 12.5 Gb/s Continuous
Lock-Range Operation
• 50 mV Input Sensitivity
• Supply Voltage: 3.3V (Typ)
• Total Power Dissipation:
1.6W (Typ)
• 15x15mm Low Profile 90 Ball
TBGA (Taped BGA) Package
• Operating Temperature Range:
0°C to +90°C (case)
General Description
The VCS8184 combines a clock re-
covery unit and data retiming with a
1:16 Demultiplexer on a single chip to
directly generate 16-bit wide data from
an incoming 11.5Gb/s to 12.5Gb/s data
stream, for use in SONET STS-192/
SDH STM-64 systems. An on-chip
Phase Locked Loop (PLL) with Volt-
age Controlled Oscillator (VCO) gen-
erates a 11.5GHz to 12.5GHz clock,
which remains phase locked to the in-
coming data. The incoming data is
retimed and Demultiplexer into 16 par-
allel outputs. It features a highly flex-
ible reference clock input scheme. The
user can select between 180-195MHz
or 719-781MHz PECL reference clock
inputs. The input serial data sampling
point voltage threshold can be adjusted.
Additional features include a parity bit
(PARITY±) that is clocked out with the
16 parallel data, Bit Order Swap
(BITORDER) and Data Polarity Invert
(DINVERT). To assist in monitoring
device operation a Loss-of-Lock
(LOLN) alarm and no reference clock
(NOREFN) alarm are provided. The
device is packaged in a modified 90-
ball, Ball Grid Array (BGA).
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