VSC8111 Datasheet, PDF (1/26 Pages) Vitesse Semiconductor Corporation – ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Data Sheet
VSC8111
VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Features
• Operates at Either STS-3/STM-1 (155.52 Mb/s) or
STS-12/STM-4 (622.08 Mb/s) Data Rates
• Compatible with Industry ATM UNI Devices
• On Chip Clock Generation of the 155.52 Mhz
or 622.08 Mhz High Speed Clock
• Dual 8 Bit Parallel TTL Interface
• Loss of Signal (LOS) Control
• Provides Equipment, Facilities and Split Loop-
back Modes as well as Loop Timing Mode
• Meets Bellcore, ITU and ANSI Specifications for
Jitter Performance
• Single 3.3V Supply Voltage
• Low Power - 1.4 Watts Maximum
• SONET/SDH Frame Detection and Recovery
• 100 PQFP Package
General Description
The VSC8111 is an ATM/SONET/SDH compatible transceiver integrating an on-chip clock multiplication
unit (PLL) for the high speed clock and 8 bit serial-to-parallel and parallel-to-serial data conversion. The high
speed clock generated by the on-chip PLL is selectable for 155.52 or 622.08 MHz operation. The demultiplexer
contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip-
ment loopback modes and two loop timing modes. The part is packaged in a 100 PQFP with an integrated heat
spreader for optimum thermal performance and reduced cost. The VSC8111 provides an integrated solution for
ATM physical layers and SONET/SDH systems applications.
VSC8111 Block Diagram
EQULOOP
LOSTTL
LOSPOL
LOS (Internal Signal)
RXDATAIN+/-
DQ
RXCLKIN+/-
0
1
FRAMER
OOF
FP
0
1:8
8
DEMUX
DQ
RXOUT[7:0]
1
0
Divide-by-8
1
RXLSCKOUT
TXDATAOUT+/-
TXCLKOUT+/-
FACLOOP
1
QD
0
1
0
10
8:1
MUX
8
QD
Divide-by-8
TXIN[7:0]
TXLSCKIN
TXLSCKOUT
Divide-by-3/12
RX50MCK
LOOPTIM0
1
CMU
0
REFCLK
LOOPTIM1
LOS
EQULOOP
G52142-0, Rev 4.2
8/31/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
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