SIP12202 Datasheet, PDF (9/10 Pages) Vishay Siliconix – Synchronous Step Down Controller

Compensation:
New Product
SiP12202
Vishay Semiconductors
VIN
VOUT
R1
FB
GM
R2
0.6 V
Compensation
PWM Comp
R3
C2
C1
OSC
500KHz
∆Vosc
L
VOUT
COUT
ESR
The SiP12201 uses voltage mode control in conjunction
with a high frequency Transconductance error amplifier.
The voltage feedback loop is compensated at the Comp/
SD pin, which is the output node of the error amplifier.
The feedback loop is generally compensated with an RC
+ C (one pole, one zero) network from comp to GND.
Loop stability is affected by the values of the inductor,
the output capacitor, the output capacitor ESR, and the
error amplifier compensation network.
The ideal Bode plot for a compensated system would be
gain that rolls off at a slope of -20 dB/decade, crossing
0dB at the desired bandwidth and a phase margin
greater than 90° for all frequencies below the 0dB cros-
sing.
The compensation network used with the error amplifier
must provide enough phase margin at the 0dB cross-
over frequency for the overall open-loop transfer func-
tion to be stable. The following guidelines will calculate
the compensation pole and zero to stabilize the
SiP12201.
The inductor and output capacitor values are usually
determined by efficiency, voltage and current ripple
requirements. The inductor and the output capacitor cre-
ate a double pole at the frequency and a -180° phase
change:
fp(LC) =
1
2π L * COUT
The ESR of the output capacitor and the output capaci-
tor value form a zero at the frequency:
f = Z(ESR)
1
2π(ESR)(COUT)
The f_Z(ESR) typically should be higher than the f_p(LC) and
give a 90° phase boost. R3 and C1 will establish the sec-
ond zero of the system. The frequency of the zero
should be 2X lower than the double pole frequency of
the inductor and the output capacitor.
fZ(comp) =
1
2πR3C1
Choose a value for R3 usually between 1 kΩ and 10 kΩ.
This second zero will provide the second 90° phase
boost and will stabilize the closed loop system.
The second pole should be placed at ½ the switching
frequency.
C2=
C1
2π
∗
R1∗ C1∗
F -1
SW
Although a mathematical approach to frequency com-
pensation can be used, the added complication of input
and/or output filters, unknown capacitor ESR, and gross
operating point changes with input voltage, load current
variations, all suggest a more practical empirical me-
thod. This can be done by injecting at the load a variable
frequency small signal voltage between the output and
the feedback network and using an RC network box to
iterate toward the final values; or by obtaining the opti-
mum loop response using a network analyzer to mea-
sure the loop Gain and Phase.
Layout:
As in the design of any switching dc-to-dc converter,
driver careful layout will ensure that there is a successful
transition from design to production. One of the few
drawbacks of switching dc-to-dc converters is the noise
induced by their high-frequency switching. Parasitic
inductance and capacitance may become significant
when a converter is switching at 500 kHz. However,
Document Number: 73542
S-52083–Rev. A, 10-Oct-05
www.vishay.com
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