SI9118_11 Datasheet, PDF (9/11 Pages) Vishay Siliconix – Programmable Duty Cycle Controller

Si9118, Si9119
Vishay Siliconix
DETAILED OPERATIONAL DESCRIPTION (CONT’D)
Programmable Duty Cycle Control
The maximum duty cycle limit is controlled by the
voltage on D_MAX pin. A D_MAX voltage of 3.2 V
generates 80 % duty cycle while 0.0 V generates
0 % duty cycle. The 80 % duty cycle is maximum
default condition at 1 MHz switching frequency. The
D_MAX voltage can be easily generated using resistor
divider from the reference voltage.The maximum duty
cycle limitation will be different when the converter is
synchronized by an external frequency. If the internal
free running frequency is much slower than the
external SYNC signal (SYNC signal causes the
internal clock to reset before the Cosc voltage ramps
to 3.2 V) , duty cycle is determined by the one shot
discharge time of the oscillator capacitor (100 ns).
Therefore, with 1 MHz SYNC signal, maximum duty
cycle of 90 % can be achieved (100 ns is 10 % of
1 MHz). If the internal free running frequency is very
close to the external SYNC frequency (SYNC signal
causes the internal clock to reset somewhere between
3.2 V to 4 V), duty cycle is determined by the ratio of
C_osc voltage at the SYNC point and the 3.2 V. At this
condition, the maximum duty cycle can be greater than
90 %. Therefore, D_MAX voltage must be modified in
order to maintain desired maximum duty cycle.
Slope Compensation
Slope compensation is necessary for duty cycles
greater than 50 % to stabilize the inner current loop
and maintain overall loop stability. In order to simplify
the slope compensation circuitry, the Si9118 provides
the buffered oscillator ramp signal, V_SC to be used for
external slope compensation. V_SC is only available
when DR is high. The V_SC signal super-imposed with
actual current sense signal should be used by the
PWM comparator to determine the duty cycle. The
summation of this signal should be fed into I_CS pin. For
optimum performance, proper slope compensation is
required. The amount of slope compensation is
determined by the resistors connected to the I_CS pin.
The amplitude of the V_SC signal is same as the C_OSC
pin voltage (4 V). For designs which use with SYNC
pin, instead of V_SC pin, the converter can still operate
at duty cycles greater than 50 % by generating an
external slope compensation ramp using a
simple RC circuit from the MOSFET driver output pin
as shown on the application circuit.
Over Current Protection
Si9118/Si9119 are designed with a pulse-to-pulse
peak
current limiting protection circuit to protect itself, and
the load in case of a failure. The voltage across the
sense resistor is monitored continuously and if the
voltage reaches its trigger level, the duty cycle is
terminated. This limits the maximum current delivered
to the load. In order to improve the accuracy of over
current protection from traditional controllers, Si9118/
Si9119 are designed with separate I_LIMIT and I_CS pins.
Voltage on the I_LIMIT pin does not sum in the traditional
slope compensation voltage, which adds error into the
detection level. I_CS pin is used to sum the current
sense signal and the slope compensation for loop
stability.
Output Driver Stage
The DR pin is designed to drive a low-side N-Channel
MOSFET. The driver stage is sized to sink and source
peak currents up to 500 mA with V_CC = 12 V. This
provides ample drive capability for 50 W of output
power.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see www.vishay.com/ppg?70815.
Document Number: 70815
www.vishay.com
S11-0975–Rev. E, 16-May-11
9
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000