SI9113_04 Datasheet, PDF (8/13 Pages) Vishay Siliconix – High-Voltage Current Mode PWM Controller for ISDN Power Supplies

Si9113
Vishay Siliconix
ǒ Ǔ DV_IN +
R₄
R₅
V_UVSTART
(3)
V_CC Circuit
The depletion MOSFET process allows the Si9113 controller
to power directly from the high input bus voltage. Once
V_UVSTART is met, the pre-regulator start-up circuit generates
the 9.0-V V_CC voltage. The V_CC voltage is used internally to
power the IC as well as providing the drive current for the
external MOSFET. An internal V_CC circuit is disabled once a
higher external voltage (X10 V) is applied to this pin. If V_CC is
below V_CCUV, the Si9113 will inhibit the driver output switching.
REF
The reference voltage of Si9113 is set at 1.3 V. The reference
voltage is internally connected to the non-inverting input of
error amplifier. The reference is decoupled with 0.1-mF
capacitor.
Soft-Start
The soft-start circuit provides a constant 10-mA current to
external capacitor attached to SS pin. A constant soft-start
current forces a gradual increase in duty cycle which in turn
ensures gradual output voltage rise without overshooting. The
soft-start time is programmed by the capacitance value.
Oscillator
The oscillator consists of a ring of CMOS inverters, capacitors,
and a capacitor discharge switch. An external resistor, R_OSC,
between the OSC_IN and OSC_OUT pins sets the frequency. The
maximum frequency is obtained when R_OSC = 0 W. A
frequency divider in the logic section limits the switch duty
cycle to 50% by locking the switching frequency to one-half of
the oscillator frequency.
PWM Mode
As the load and line voltage vary, the switching frequency
remains constant. The switching frequency is programmed by
the R_OSC value as shown by the oscillator curve. In the PWM
mode, a duty cycle pulse is generated for each switching
period eliminating any chance of undesirable noise frequency.
When the output load current decreases to 0 A, the controller
is forced to enter the pulse skipping mode. This is a natural
phenomenal for all controllers since the duty cycle cannot
decrease linearly to 0%.
Error Amplifier
The error amplifier gain-bandwidth product and slew rate are
critical parameters which determine the transient response of
converter. The transient response is the function of both small
and large signal responses. The small signal response is
determined by the converter closed loop bandwidth and phase
margin while the large signal is determined by the error
amplifier dv/dt and the inductor di/dt slew rate. Besides the
inductance value, the error amplifier determines the converter
response time. In order to minimize the response time, the
Si9113 is designed with 1.3-MHz error amplifier
gain-bandwidth product to generate the widest converter
bandwidth.
Current Limit
Over current protection circuit is provided by monitoring the
voltage on the Sense pin. Once the current sense voltage
reaches 0.6V peak, the output drive stage is disabled for the
remainder of the clock cycle.
Power_Good Comparator
The PWR_Good signal indicates the status of output voltage.
If the output voltage and V_CC are within regulation, the
PWR_Good signal generates a logic high output by monitoring
the voltage on COMP and V_CC pins. If either one is out of
regulation, a logic low PWR_Good signal is generated. The
capacitor at the PWR_Good pin determines the rise time of the
power good signal, once all the conditions are met for power
good. The PWR_Good signal is an open collector output
capable of sinking 2.5 mA.
MOSFET Gate Drive
The DRIVER pin is designed to drive the low-side n-channel
MOSFET. Typically, the driver stage is sized to sink and source
200-mA of peak current when V_CC = 12 V.
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Document Number: 71093
S-40746—Rev. B. 19-Apr-04