DG441L_11 Datasheet, PDF (8/14 Pages) Vishay Siliconix – Precision Monolithic Quad SPST Low-Voltage CMOS Analog Switches

DG441L, DG442L
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
5 V Reg
Level
IN_X
Shift/
Drive
GND
V-
TEST CIRCUITS
Figure 1.
S
V-
V+
D
V+
V+
V_S
S
D
IN
3V
R_L
1 k
GND
V-
V_O
C_L
35 pF
V-
C_L (includes fixture and stray capacitance)
Logic
3V
Input
0V
Switch _VS
Input
50 % 50 %
t_r < 20 ns
t_f < 20 ns
t_OFF
V_O
80 %
80 %
Switch 0 V
Output
t_ON
Note:
Figure 2. Switching Time
Logic input waveform is inverted for DG442.
V+
V+
R_g
S
D
IN
3V
GND
V-
V-
V_O
C_L
1 nF
V_O
IN_{X OFF}
(DG441)
OFF
IN_X
(DG442)
V
O
ON
OFF
ON
Q = V_O x C_L
OFF
Figure 3. Charge Injection
www.vishay.com
Document Number: 71399
8
S11-1066–Rev. E, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000