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DG417L_08 Datasheet, PDF (8/11 Pages) Vishay Siliconix – Precision Monolithic Low-Voltage CMOS Analog Switches
DG417L/418L/419L
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
VL
VIN
GND
V-
TEST CIRCUITS
Level
Shift/
Drive
Figure 1.
S
V-
V+
D
Switch
Input
VIN
VL
VL
NO or NC
IN
GND
V+
V+
COM
V-
Switch
Output
VOUT
RL
300 Ω
CL
35 pF
Logic
Input
VINH
VINL
Switch
0V
Output
50 %
tr < 5 ns
tf < 5 ns
tOFF
VOUT
90 %
0.9 x VOUT
tON
V-
CL (includes fixture and stray capacitance)
VOUT = VIN
RL
RL + rON
Note: Logic input waveform is inverted for switches that
have the opposite logic sense control
Figure 2. Switching Time
VNO
VNC
VL
VL
NO
NC
IN
V+
V+
COM
RL
300 Ω
Logic
Input
VO
VINH
VINL
CL
35 pF
VNC = VNO
VO
90 %
GND V-
Switch
0V
Output
tD
V-
CL (includes fixture and stray capacitance)
Figure 3. Break-Before-Make (DG419L)
tr < 5 ns
tf < 5 ns
tD
www.vishay.com
8
Document Number: 71763
S-71009–Rev. E, 14-May-07