DG201B_11 Datasheet, PDF (8/15 Pages) Vishay Siliconix – Improved Quad CMOS Analog Switches

DG201B, DG202B
Vishay Siliconix
APPLICATIONS
+ 15 V
V+
Logic Input
Low = Sample
High = Hold
+ 15 V
- 15 V
-
LM101A
V_IN
+
5 MΩ
5.1 MΩ
30 pF
Aquisition Time
Aperature Time
Sample to Hold Offset
Droop Rate
= 25 µs
= 1 µs
= 5 mV
= 5 mV/s
V-
- 15 V
DG201B
1 kΩ
50 pF
Figure 6. Sample-and-Hold
+ 15 V
J202
200 Ω
1000 pF
2N4400
J500
J507
- 15 V
V_OUT
f_C4
Select
TTL
Control
f_C3
Select
f_C2
Select
f_C1
Select
C₄
150 pF
C₃
1500 pF
C₂
0.015 µF
C₁
0.15 µF
+ 15 V
V₁
V- ^DG201B GND
R₁ = 10 kΩ
R₂ = 10 kΩ
- 15 V
R₃ = 1 MΩ
+ 15 V
-
LM101A
- 15 V
+
30 pF
160
120
80
f_C1
40
f_C2 f_C3 f_C4
0
f_L1
f_L2
f_L3
f_L4
- 40
1
10
100
1K
10K 100K 1M
f - Frequency (Hz)
V_OUT
A_L (Voltage Gain Below Break Frequency) =
1
f_C (Break Frequency) = _2πR3CX
f_L (Unity Gain Frequency) =
1
2πR₁C_X
Max. Attenuation =
R_{DS(on) ≈ - 47 dB}
10 kΩ
R₃
R₁ ^{= 100 (40 dB)}
Figure 7. Active Low Pass Filter with Digitally Selected Break Frequency
www.vishay.com
Document Number: 70037
8
S11-0800-Rev. J, 25-Apr-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000