SIC779 Datasheet, PDF (7/17 Pages) Vishay Siliconix – Integrated DrMOS Power Stage

PIN CONFIGURATION
SiC779
Vishay Siliconix
SMOD 1
VCIN 2
VDRV 3
BOOT 4
CGND 5
GH 6
PHASE 7
VIN 8
VIN 9
V_IN 10
AGND
P1
VIN
P2
V_SWH
P3
30 VSWH
29 VSWH
28 PGND
27 PGND
26 PGND
25 PGND
24 PGND
23 PGND
22 PGND
21 PGND
Figure 5 - PowerPAK MLP 6 x 6 40P Pin Out - Top View
PIN DESCRIPTION
Pin Number
Symbol
1
SMOD
2
V_CIN
3
V_DRV
4
BOOT
5, 37, PAD1
6
C_GND
GH
7
PHASE
8 to 14, PAD2
15, 29 to 35,
PAD3
V_IN
V_SWH
16 to 28
36
P_GND
GL
38
THDN
39
DSBL#
40
PWM
Description
Disable low side gate operation. Active low.
This will be the bias supply input for control IC (5 V).
IC bias supply and gate drive supply voltage (5 V).
High side driver bootstrap voltage pin for external bootstrap capacitor.
Control signal ground. It should be connected to P_GND externally. All pins internally connected.
Gate signal output pin for high side MOSFET. Pin for monitoring.
Return pin for the HS bootstrap capacitor. Connect a 0.1 µF ceramic capacitor from this pin to the boot pin (4).
Input voltage for power stage. It is the drain of the high-side MOSFET.
It is the phase node between high side MOSFET source and low side MOSFET drain. It should be connected
to an output inductor. All pins internally connected.
Power ground.
Gate signal output pin for low side MOSFET. Pin for monitoring.
Thermal shutdown open drain output. Use a 10K pull up resistor to V_CIN.
Disable pin. Active low.
PWM input logic signal. Compatible with Tristate controller function.
Document Number: 67538
www.vishay.com
S11-0703-Rev. B, 18-Apr-11
7
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000