DG441_11 Datasheet, PDF (7/14 Pages) Vishay Siliconix – Quad SPST CMOS Analog Switches

DG441, DG442
Vishay Siliconix
TEST CIRCUITS
+ 15 V
10 V
3V
V+
S
D
IN
GND
R_L
1 k
V-
- 15 V
V_O
C_L
35 pF
Logic
3V
Input
0V
Switch _VS
Input
50 % 50 %
t_r < 20 ns
t_f < 20 ns
t_OFF
V_O
80 %
80 %
Switch 0 V
Output
t_ON
C_L (includes fixture and stray capacitance)
Note:
Figure 2. Switching Time
Logic input waveform is inverted for DG442.
+ 15 V
V+
R_g
S
D
IN
3V
GND
V-
- 15 V
V_O
C_L
1 nF
Figure 3. Charge Injection
V_O
IN_{X OFF}
(DG441)
OFF
IN_X
(DG442)
V
O
ON
OFF
ON
Q = V_O x C_L
OFF
C = 1 mF tantalum in parallel with 0.01 mF ceramic
+ 15 V
C
V_S
R_g = 50 
0 V, 2.4 V
NC
0 V, 2.4 V
V+
S₁
D₁
IN₁
S₂
D₂
IN₂
GND
V-
C
50 
V_O
R_L
- 15 V
X_{TA LK} Isolation = 20 log
C = RF bypass
V_S
V_O
Figure 4. Crosstalk
+ 15 V
+ 15 V
C
V_S
V+
S
D
V_O
R_g = 50 
IN
R_L
0 V, 2.4 V
GND
V-
C
- 15 V
Off Isolation = 20 log ^VS
V_O
Figure 5. Off Isolation
C
V+
S
IN
0 V, 2.4 V
GND
D
V-
C
Meter
HP4192A
Impedance
Analyzer
or Equivalent
- 15 V
Figure 6. Source/Drain Capacitances
Document Number: 70053
www.vishay.com
S11-1066-Rev. J, 30-May-11
7
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000