DG528 Datasheet, PDF (5/10 Pages) Vishay Siliconix – Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers

SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
GND
EN
A_X
WR
RS
V–
V_REF
V+
V+
V–
V+
V–
V+
V–
D_O Q_O
V–
V+
D_n Q_n
V–
V+ ^Latches
Level
Shift
Decode
V–
V+
CLK
RESET
FIGURE 1.
DG528/529
Vishay Siliconix
S₁
S_n
V–
V+
D
DETAILED DESCRIPTION
The internal structure of the DG528/DG529 includes a 5-V
logic interface with input protection circuitry followed by a latch,
level shifter, decoder and finally the switch constructed with
parallel n- and p-channel MOSFETs (see Figure 1).
Following the latches the Q_X signals are level shifted and
decoded to provide proper drive levels for the CMOS switches.
This level shifting insures full on/off switch operation for any
analog signal present between the V+ and V– supply rails.
The logic interface circuit compares the TTL input signal
against a TTL threshold reference voltage. The output of the
comparator feeds the data input of a D type latch. The level
sensitive D latch continuously places the D_X input signal on the
Q_X output when the WR input is low, resulting in transparent
latch operation. As soon as WR returns high, the latches hold
the data last present on the D_X input, subject to the minimum
input timing requirements.
3V
WR
0
3V
A₀, A₁, (A₂)
EN
0
50%
t_W
t_S
80%
t_H
80%
FIGURE 2.
The EN pin is used to enable the address latches during the
WR pulse. It can be hard-wired to the logic supply or to V+ if one
of the channels will always be used (except during a reset) or
it can be tied to address decoding circuitry for memory mapped
operation. The RS pin is used as a master reset. All latches are
cleared regardless of the state of any other latch or control line.
The WR pin is used to transfer the state of the address control
lines to their latches, except during a reset or when EN is low
(see Truth Tables).
3V
RS
0
Switch ^VO
Output
0
50%
t_RS
t_{OFF (RS)}
FIGURE 3.
80%
Document Number: 70068
P-32167—Rev. C, 15-Nov-93
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