Y16251K00000T9R Datasheet, PDF (4/5 Pages) Vishay Siliconix – Ultra High Precision Foil Wraparound Surface Mount Chip Resistor with TCR of ± 0.05 ppm/°C and Power Coefficient of 5 ppm at Rated Power and Load Life Stability of ± 0.005 % (50 ppm)

VSMP Series (0603, 0805, 1206, 1506, 2010, 2018, 2512) (Z-Foil)
Vishay Foil Resistors
PULSE TEST
TEST DESCRIPTION
All parts are baked at +125°C for 1 hour and allowed to cool
at room temperature for 1 hour, prior to testing. By using an
electrolytic 0.01µF capacitor charged to 1200 VDC, a single
pulse was performed on 30 units of 1206, 10 k of Surface
Mount Vishay Foil resistor and Thin Film resistor. The units
were allowed time to cool down, after which the resistance
measurements were taken and displayed in ppm deviation
from the initial reading.
TEST RESULTS
FIGURE 8 - PULSE TEST DESCRIPTION
2
"#
 *+
!)
FIGURE 9 - PULSE TEST RESULTS AT
1200 VDC*
140000
120000
100000
80000
60000
40000
20000
Thin Film
Bulk Metal^® Foil
Size: 1206
Value: 10K
n = 30
0
0
-20000
5
10
15
20
25
30
Resistor #
Note: Average of 30 units yielded deviation of 30 723 ppm of the Thin Film vs –14 ppm for the Bulk Metal^® Foil
* Note: Average of 30 units yielded deviation of 30,723 ppm of the
Thin Film vs. -14 ppm for the Bulk Metal^® Foil
ELECTROSTATIC DISCHARGE (ESD)
ESD can be categorized into three types of damages:
Parametric Failure - occurs when the ESD event alters one
or more device parameters (resistance in the case of
resistors), causing it to shift from its required tolerance. This
failure does not directly pertain to functionality; thus a
parametric failure may be present while the device is still
functional.
Catastrophic Damage - occurs when the ESD event causes
the device to immediately stop functioning. This may occur
after one or a number of ESD events with diverse causes,
such as human body discharge or the mere presence of an
electrostatic field.
Latent Damage - occurs when the ESD event causes
moderate damage to the device, which is not noticeable, as
the device appears to be functioning correctly. However, the
load life of the device has been dramatically reduced, and
further degradation caused by operating stresses may cause
the device to fail during service. Latent damage is the source
for greatest concern, since it is very difficult to detect by
re-measurement or by visual inspection, because damage
may have occurred under the external coating.
TEST DESCRIPTION
By using an electrolytic 500 pF capacitor charged up to 4500
V, pulses were performed on 10 units of 1206, 10 k of three
different Surface Mount Chip Resistors technologies, with an
initial voltage spike of 2500 V (Figure 10). The units were
allowed time to cool down, after which the resistance
measurements were taken and displayed in ppm deviation
from the initial readings. Readings were then taken in 500 V
increments up to 4500 V.
FIGURE 10 - ESD TEST DESCRIPTION
2500 V to 4500 V
1 MΩ
500 pF
Rx
DMM
TABLE 6 - ESD TEST RESULTS 
(AVERAGE OF 10 UNITS)
VOLTS
THICK FILM
∆R (%)
THIN FILM
FOIL
2500
-2.7
97
<0.005
3000
-4.2
366
<0.005
3500
-6.2
OPEN
<0.005
4000
-7.4
OPEN
<0.005
4500
-8.6
OPEN
<0.005
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Document Number: 63060
Revision: 29-Oct-2012