SI9978 Datasheet, PDF (4/6 Pages) Vishay Siliconix – Configurable H-Bridge Driver

Si9978
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
V_{DD 1}
EN/EN_A 2
DIR/IN_{A 3}
PWM/EN_B 4
QS/IN_B 5
MODE ₆
BRK 7
CL/FAULT_B 8
FAULT/FAULT_A 9
NC ₁₀
R_A/C_{A 11}
R_B/C_{B 12}
SO-24
(Wide Body)
Top View
24 ^V+
23 CAPA
22 ^SA
21 ^GTA
20 ^GBA
19 ^CAPB
18 ^SB
17 ^GTB
16 ^GBB
15 ^GND
14 ^ILB⁺
13 ^ILA⁺
ORDERING INFORMATION
Lead (Pb)-Free Temperature
Part Number Part Number
Range
Package
Si9978DW
Si9978DW-T1
Si9978DW-T1—E3
−40 to 85_C
SOIC-24
(Wide Body)
PIN DESCRIPTION
Pin 1: V_DD
V_DD is an internally generated voltage. It is connected to this
pin to allow connection of a decoupling capacitor. A minimum
of 1 mF is recommended.
Pin 2: EN/EN_A
The EN input allows normal operation when at logic “1”, and
turns all gate drive outputs off when at logic “0”. When the
mode pin is at logic “1”, EN controls the entire H-bridge. When
the mode pin is at logic “0”, this pin becomes the ENABLE pin
for half-bridge A.
Pin 3: DIR/IN_A
The function of this pin is determined by the MODE pin. When
the MODE pin is at logic “1”, it is the DIR pin, and when MODE
is at logic “0”, it is the IN_A pin.
As the DIR input, it is the direction control for the H-bridge, and
determines which diagonal pair of power MOSFETs is active.
A logic “1” turns on GT_A and enables GB_B, while a logic “0”
turns on GT_B and enables GB_A. When implementing an
anti-phase PWM control, the DIR input serves as the PWM
input.
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4
As the IN_A pin, it is the input that controls the “A” half-bridge.
When at logic “1”, the high-side MOSFET is turned on, and
when at logic “0”, the low-side MOSFET is turned on.
Pin 4: PWM/EN_B
With the mode pin at logic “1”, this pin is the PWM input. It
controls the switching of the active diagonal pair. A logic “1”
turns the active MOSFETs on, while a logic “0” turns it off. The
QS input determines whether the bottom or both bottom and
top MOSFETs are switched. When implementing an
anti-phase PWM control, the PWM input is connected to a logic
“1”. When the mode pin is at logic “0”, this pin becomes the
ENABLE pin for half-bridge B.
Pin 5: QS/IN_B
With the mode pin at logic “1”, this input determines whether
the bottom MOSFETs of the H-bridge or both bottom and top
MOSFETs switch in response to the PWM signal. A logic “1” on
this input enables only the bottom MOSFETs. This is the
default condition as this pin is pulled up internally. When this
pin is pulled to ground, both the bottom and top MOSFETs are
enabled.
This input controls the B half-bridge when the MODE pin is at
logic “0”. When at logic “1”, the high-side MOSFET is turned on,
and when at logic “0”, the low-side MOSFET is turned on.
Document Number: 70011
S-40804—Rev. E, 26-Apr-04