SI9183_05 Datasheet, PDF (4/11 Pages) Vishay Siliconix – High-Performance, Size Saving 150-mA CMOS LDO Regulator

Si9183
Vishay Siliconix
TIMING WAVEFORMS
V_IN
t_ON
0.95 V_NOM
V_OUT
V_NOM
FIGURE 3. Timing Diagram for Power-Up
PIN CONFIGURATION
Thin SOT-23, 5-Pin
V_IN 1
5 V_OUT
GND 2
SD 3
4 ^{BP (Version A)}
FB (Version B)
PIN DESCRIPTION
Pin Number
Name
1
V_IN
2
GND
3
SD
4 (Version A)
BP
4 (Version B)
5
FB
V_OUT
Function
Input supply pin. Bypass this pin with a 1-mF ceramic or tantalum capacitor to ground.
Ground pin. Local ground for C_BP and C_OUT.
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to V_IN if unused.
Noise bypass pin. For low noise applications, a 0.1-mF or larger ceramic capacitor should be connected from this pin to
ground.
Connect to divided output voltage to adjust the regulation point.
Output voltage. Connect C_OUT between this pin and ground.
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4
Document Number: 71258
S-51147—Rev. G, 20-Jun-05