SI91821 Datasheet, PDF (4/10 Pages) Vishay Siliconix – Micropower 300-mA CMOS LDO Regulator With Error Flag

Si91821
Vishay Siliconix
TIMING WAVEFORMS
V_IH
SD
V_IL
t_ON
V_{NOM =} 0.95 V_NOM
V_OUT
ERROR
t_DELAY
t_DELAY
Figure 4. Timing Diagram for Power-Up
PIN CONFIGURATION
v_OUT
1
v_IN
2
GND
3
V_OUT
4
MSOP-8
Top View
8
ERROR
7
SD
6
C_NOISE
5
SET
PIN DESCRIPTION
Pin Number
Name
1, 4
V_OUT
2
V_IN
3
GND
5
SET
6
C_NOISE
7
SD
8
ERROR
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4
Function
Output voltage. Connect C_OUT between this pin and ground.
Input supply pin. Bypass this pin with a 2.2-mF ceramic or tantalum capacitor to ground.
Ground pin. Local ground for C_NOISE and C_OUT.
For fixed output voltage versions, this pin could be connected to GND. For adjustable output voltage version, this
voltage feedback pin sets the output voltage via an external resistor divider.
Noise bypass pin. For low noise applications, a 0.01-mF or larger ceramic capacitor should be connected from this pin
to ground.
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to V_IN if unused.
This open drain output is an error flag output which goes low when V_OUT drops 5% below its nominal voltage.
Document Number: 71614
S-51147–Rev. E, 20-Jun-05