SI9181 Datasheet, PDF (4/10 Pages) Vishay Siliconix – Micropower 350-mA CMOS LDO Regulator With Error Flag/Power-On-Reset

Si9181
Vishay Siliconix
TIMING WAVEFORMS
PIN CONFIGURATION
V_IN
t_ON
0.95 V_NOM
V_OUT
V_NOM
ERROR
t_DELAY
FIGURE 4. Timing Diagram for Power-Up
C_NOISE 1
DELAY 2
GND 3
V_IN 4
TSSOP-8
Top View
8 SD
7 ERROR
6 SENSE or ADJ
5 VOUT
PIN DESCRIPTION
Pin Number
Name
1
C_NOISE
2
DELAY
3
GND
4
V_IN
5
V_OUT
6
SENSE or ADJ
7
ERROR
8
SD
Function
Noise bypass pin. For low noise applications, a 0.01-mF or larger ceramic capacitor should be connected from this pin
to ground.
Capacitor connected from this pin to ground will allow a delayed power-on-reset signal at the ERROR (Pin 7) output.
Refer to Figure 4.
Ground pin. Local ground for C_NOISE and C_OUT.
Input supply pin. Bypass this pin with a 2.2-mF ceramic or tantalum capacitor to ground.
Output voltage. Connect C_OUT between this pin and ground.
For fixed output voltage versions, this pin should be connected to V_OUT (Pin 5). For adjustable output voltage version,
this voltage feedback pin sets the output voltage via an external resistor divider.
This open drain output is an error flag output which goes low when V_OUT drops 5% below its nominal voltage. This pin
also provides a power-on-reset signal if a capacitor is connected to the DELAY pin.
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to V_IN if unused.
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Document Number: 71119
S-40694—Rev. D, 19-Apr-04