SI9150 Datasheet, PDF (4/5 Pages) Vishay Siliconix – Synchronous Buck Converter Controller

Si9150
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
SOIC
EN 1
STANDBY 2
SS 3
COMP 4
FB 5
V_REF 6
I_SENSE 7
Top View
14 VDD
13 P-GATE
12 N-GATE
11 GND
10 RT
9 CT
8 SYNC
ORDERING INFORMATION
Part Number Temperature Range
Package
Si9150CY
Si9150CY-T1
Si9150CY-T1—E3
Si9150DY
Si9150DY-T1
Si9150DY-T1—E3
0 to 70_C
−40 to 85_C
SOIC-14
PIN DESCRIPTION
Pin 1: EN
When this pin is low, the IC is shut down. After a low signal is
applied to EN, then COMP, REF, R_T, and C_T settle toward
ground; N-GATE, STBY and Soft-Start are grounded; and
P-GATE is pulled high. The current consumption is no more
than 100 mA in this state. This input’s threshold has substantial
hysteresis so that a capacitor to GND can be used to delay
restart after the current limit is activated. After V_ENH is
exceeded, one clock cycle elapses before N-GATE and
P-GATE are enabled. EN is pulled up to V_DD through a 500-k
resistor and is pulled down internally when the current limit is
triggered.
Pin 2: STBY
Has a function similar to EN. The differences are that the EN
pin is unaffected, that the reference is still available, that bias
currents are still present internally, and that this pin’s pull up
current is present. This pin should be used to disable an
application if the reference voltage is still needed.
Pin 3: Soft-Start (SS)
This pin limits the maximum voltage that the error amplifier can
output. A capacitor between this pin and ground will limit the
rate at which the duty factor can increase during initial power
up, during a restart when EN or STBY goes high, or after the
current limit is triggered. A capacitor here can prevent an
application from triggering the Si9150’s current limit during
startup. Soft-Start is pulled low if either EN or STBY is low.
Pin 4: Compensation (COMP)
This pin is tied directly to the output of the error amplifier. The
feedback network which insures the stability of an application
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4
uses this pin. COMP settles low when either EN or STBY is
pulled low.
Pin 5: Feedback (FB)
This pin is attached directly to the inverting input of the error
amplifier. This pin is used to regulate the power supply’s output
voltage.
Pin 6: Reference (V_REF)
The internal 2.5-V reference generator is attached to this pin
through a 5-W resistor. A 0.1-mF bypass capacitor is needed to
suppress noise. Also note that the generator has an open
emitter; it will not pull down. The maximum current that the
generator will source before it current limits is about 10 mA.
Many parts of the IC use this voltage, so it is important not to
overload the reference generator.
Pin 7: I_SENSE
This pin should be attached to the switched node (the drains
of the application’s p-channel and n-channel MOSFETs). If the
voltage between V_DD and this pin is more then 0.46 V while the
P-GATE is low, the current limit is activated. The current limit
is relatively slow to prevent false triggering due to noise.
Activating the current limit causes EN to be pulled to GND.
I_SENSE may be operated from V_DD + 2 V to GND − 2 V. For
operation above 13.5 V_DD a filter (1 kW, 33 pF) is needed
between the MOSFET drains and the I_SENSE pin; refer to
Figure 1.
Pin 8: SYNC
This pin forces the clock to reset when low, and is also pulled
low when the clock resets itself. Thus if several Si9150’s have
their sync pins shorted together, they will be synchronized; the
shortest duration clock will control the other clocks.
Document Number: 70020
S-40752—Rev. F, 19-Apr-04