ACAC0612 Datasheet, PDF (4/5 Pages) Vishay Siliconix – Flat Chip Resistor Array

ACAC 0612 - Precision
Vishay Beyschlag
Flat Chip Resistor Array
TESTS AND REQUIREMENTS
Essentially all tests are carried out in accordance with the
following specifications:
EN 140 000 / EN 60 115-1, Generic specification
(includes tests)
EN 140 400 / EN 60 115-1, Sectional specification
(includes schedule for qualification approval)
The testing also covers most of the requirements specified
by EIA/IS-703 and JIS-C-5202.
The tests are carried out in accordance with IEC 60 068
and under standard atmospheric conditions according to
IEC 60 068-1, 5.3. Climatic category LCT/UCT/56 (rated
temperature range: Lower Category Temperature, Upper
Category Temperature; damp heat, long term, 56 days) is
valid.
Unless otherwise specified the following values apply:
Temperature: 15 °C to 35 °C
Relative humidity: 45 % to 75 %
Air pressure: 86 kPa to 106 kPa (860 mbar to 1 060 mbar).
The components are mounted for testing on boards in
accordance with EN 60 115-1, 4.31 unless otherwise
specified.
In the following table only the tests and requirements are
listed with reference to the relevant clauses of EN 60 115-1
and IEC 60 068-2; a short description of the test procedure
is also given.
TEST PROCEDURES AND REQUIREMENTS
EN
60 115-1
CLAUSE
IEC
60 068-2
TEST
METHOD
TEST
PROCEDURE
stability for product types:
ACAC 0612
4.5
−
resistance
−
4.8.4.2
−
temperature coefficient
at 20 / LCT / 20 °C and
20 / UCT / 20 °C
4.25.1
−
endurance
U = P₇₀ × R
or U = U_max;
1.5 h on; 0.5 h off;
70 °C; 1000 h
4.25.3
4.24
4.13
4.19
4.18.2
4.17.2
4.32
4.7
−
78 (Cab)
−
14 (Na)
58 (Tb)
58 (Ta)
21 (Ue₃)
−
endurance at upper
category temperature
damp heat,
steady state
short time overload²⁾
rapid change of
temperature
resistance to soldering
heat
solderability
shear (adhesion)
voltage proof
125 °C; 1000 h
(40 ± 2) °C; 56 days;
(93 ± 3) % RH
U = 2.5 × P₇₀ × R or
U = 2 × U_max; 5 s
30 min. at LCT and
30 min. at UCT; 5 cycles
reflow method 2 (IR / forced gas
convention); (260 ± 5) °C;
(10 ± 1) s
solder bath method;
(215 ± 3) °C;
(3 ± 0.3) s
RR 1632M; 45 N
U_rms = U_ins;
60 ± 5 s; against ambient,
between adjacent resistors
Note
1. Figures are given for equal values.
2. For a single element.
REQUIREMENTS¹⁾
PERMISSIBLE CHANGE (∆R/R)
100 Ω to 221 kΩ
± 0.25 %
± 25 ppm/K
± (0.25 % R + 0.05 Ω)
± (0.5 % R + 0.05 Ω)
± (0.5 % R + 0.05 Ω)
± (0.1 % R + 0.01 Ω)
no visible damage
± (0.1 % R + 0.01 Ω)
no visible damage
± (0.1 % R + 0.01 Ω)
no visible damage
good tinning (≥ 95 % covered);
no visible damage
no visible damage
no flashover or breakdown
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Document Number: 28741
Revision: 28-Nov-05