Y40625K00000Q0R Datasheet, PDF (3/7 Pages) Vishay Siliconix – Ultra High Precision Foil Wraparound Surface Mount Chip Resistor

FIGURE 2 - TRIMMING TO VALUES
(Conceptual Illustration)
Interloop Capacitance
Reduction in Series
Mutual Inductance
Reduction due
to Change in
Current Direction
Current Path
Before Trimming
Current Path
After Trimming
Trimming Process
Removes this Material
from Shorting Strip Area
Changing Current Path
and Increasing
Resistance
Note: Foil shown in black, etched spaces in white
To acquire a precision resistance value, the Bulk Metal^® Foil
chip is trimmed by selectively removing built-in “shorting bars.”
To increase the resistance in known increments, marked areas
are cut, producing progressively smaller increases in resistance.
This method reduces the effect of “hot spots” and improves the
long term stability of the Vishay Foil chips.
TABLE 4 - SPECIFICATIONS⁽¹⁾
CHIP
SIZE
RATED
WORKING
POWER (mW) POWER (mW)
at + 70°C
at + 200 °C*
RESISTANCE
RANGE
()
0603
120
33
100 to 5K
0805
300
83
10to 8K
1206
500
140
10to 25K
1506
600
167
10to 30K
2010
800
220
10 to 70K
2512
1200
330
10to 125K
Note
* _{Maximum working voltage for a given resistance value is calculated}
using V = P  R .
TABLE 2- DIMENSIONS AND LAND PATTERN in Inches (Millimeters)
Top View
L
Recommended Land Pattern*
T
W
Extended Pads
D
CHIP
SIZE
L
W
THICKNESS
± 0.005 (0.13) ± 0.005 (0.13) MAXIMUM
0603
0.063 (1.60)
0.032(0.81)
0.025 (0.64)
0805
0.080 (2.03)
0.050 (1.27)
0.025 (0.64)
1206
0.126 (3.20)
0.062 (1.57)
0.025 (0.64)
1506
0.150 (3.81)
0.062 (1.57)
0.025 (0.64)
2010
0.198 (5.03)
0.097 (2.46)
0.025 (0.64)
2512
0.249 (6.32)
0.127 (3.23)
0.025 (0.64)
* For 0603 and 0805 land pattern dimensions are per IPC-782
D
± 0.005 (0.13)
0.011 (0.28)
0.015 (0.38)
0.035 (0.89)
0.047 (1.20)
0.071 (1.82)
0.095 (2.43)
G
Z
Z
0.102 (2.59)
0.122 (3.10)
0.175 (4.45)
0.199 (5.05)
0.247 (6.27)
0.291 (7.39)
Footprint
X
G
0.031 (0.78)
0.028 (0.71)
0.029 (0.74)
0.029 (0.74)
0.029 (0.74)
0.029 (0.74)
X
0.031 (0.78)
0.050 (1.27)
0.071 (1.80)
0.071 (1.80)
0.103 (2.62)
0.127 (3.23)
TABLE 3 - COMPARATIVE PERFORMANCES⁽²⁾ - THIN FILM VS. BULK METAL^® Z1-FOIL
TECHNOLOGY
TEST OR CONDITIONS
Thermal Shock, 5 x (- 65 °C to + 200 °C)
R LIMITS OF
THIN FILM
(TYPICAL)
± 0.1 %
R LIMITS OF
BULK METAL^®
Z1-FOIL TECHNOLOGY -
FRSH SERIES⁽¹⁾
(TYPICAL)
± 0.05% (500 ppm)
Low Temperature Operation, - 65 °C, 45 min at Rated Power
± 0.1 %
± 0.0025% (25 ppm)
Moisture Resistance
Load Life Stability, + 200 °C for 2000 h at Working Power (see table 4)
Long term stability, + 225 °C for 2000h, no power.
Notes
(1) _{Performances obtained with ceramic PCB.}
(2) _{As shown + 0.01  to allow for measurement errors at low values.}
± 0.1 %
± 0.5 %
± 0.5 %
± 0.003% (30 ppm)
± 0.05% (500 ppm)
± 0.05 % (500 ppm)
Document Number: 63211
Revision: 20-Mar-12
For any questions, contact: [e-mail]
www.vishayfoilresistors.com
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