VBUS54DD-HS4 Datasheet, PDF (3/5 Pages) Vishay Siliconix – 4-Line BUS-port ESD-protection

VBUS54DD-HS4
4-Line BUS-port ESD-protection _{Vishay Semiconductors}
1.0
0.9
f = 1 MHz
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Pin 1, 3, 4 or 5 to pin 2 and 6
(one of pin 1, 3, 4 or 5 connected to 3.3 V)
00
1
2
3
4
5
6
V_R (V)
Fig. 3 - Typical Capacitance C_D vs. Reverse Voltage V_R
100
10
1
0.1
0.01
0.001
0.5
Pin 2 and 6 to pin 1, 3, 4, or 5
0.6 0.7 0.8 0.9 1.0 1.1
V_F (V)
Fig. 4 - Typical Forward Current I_F vs. Forward Voltage V_F
9
8
7
Pin 1, 3, 4 or 5 to pin 2 and 6
6
5
4
3
2
1
0
0.01 0.1
1
10¹ 10²
I_R (µA)
10³ 10⁴
Fig. 5 - Typical Reverse Voltage V_R vs.
Reverse Current I_R
20
Measured acc. IEC 61000-4-5
(8/20µs - wave form)
15
10
V_C
5
Pin 1, 3, 4 or 5 to pin 2 and 6
0
-5
0
1
2
3
4
I_PP (A)
Fig. 6 - Typical Peak Clamping Voltage V_C vs.
Peak Pulse Current I_PP
120
Acc. IEC 61000-4-2
100
+ 8 kV
contact discharge
80
Pin 1, 3, 4 or 5 to pin 2 and 6
60
40
20
0
- 20
- 10 0 10 20 30 40 50 60 70 80 90
t (ns)
Fig. 7 - Typical Clamping Performance at + 8 kV
Contact Discharge (acc. IEC 61000-4-2)
180
160
Acc. IEC 61000-4-2
- 8 kV
140
contact discharge
120
100
Pin 1, 3, 4 or 5 to pin 2 and 6
80
60
40
20
0
- 20
- 10 0 10 20 30 40 50 60 70 80 90
t (ns)
Fig. 8 - Typical Clamping Performance at - 8 kV
Contact Discharge (acc. IEC 61000-4-2)
Document Number: 83384
Rev. 1.0, 18-Apr-11
For technical questions, contact: [e-mail]
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000