71117 Datasheet, PDF (3/11 Pages) Vishay Siliconix – SI9113 Demonstration Board

Si9113DB
Vishay Siliconix
Output Regulation
The output regulation of slave outputs depend upon the
loading condition of main output.
In Si9113D1, the V_OUT1 (3.3 V) is tightly regulated to within 1%,
while V_OUT2 (40 V) follows the main output. Figure 2 depicts
the typical load regulation of 40 V output, when the main output
is at 10% and at full load condition.
In Si9113D2, the V_OUT1 and V_OUT2 are both moderately
regulated. Figures 3 and 4 show the 3.3-V and 40-V regulation
with the outputs loaded at 10% to100% of the rated load. The
3.460
3.420
3.380
3.340
40 V @ 12 mA
3.300
40 V @ 1.2 mA
3.260
3.220
3.180
3.140
0
25
50
75
100 125 150
I_OUT1 (mA)
FIGURE 3. V_OUT1 (3.3 V) Load/cross Regulation – Si9113D2
output voltages are essentially constant with respect to any
variation of input voltage in case of both demo boards.
Output Ripple and Noise
The tantalum chip capacitors are used for lower ESR and
higher ripple current capability. Low cost aluminium capacitors
can also be used where form fator and/or output ripple are of
secondary importance. Also, a small additional LC filter can be
added at 3.3-V output for further attenuation of ac component
by even five to ten times. The Si9113D1 – Figure 5 and
Si9113D2 – Figure 6 show the ripple at a full load and 48-V
input.
42.00
41.50
41.00
40.50
40.00
39.50
39.00
3.3 V @ 12 mA
3.3 V @ 120 mA
38.50
38.00
0
3.00
6.00
9.00
12.00 15.00
I_OUT2 (mA)
FIGURE 4. V_OUT2 (40 V) Load/Cross Regulation – Si9113D2
V_IN = 48 V
Outputs = At Full Load
Ch1 = 3.3 V (20 mV/div))
Ch3 = 40 V (100 mV/div)
FIGURE 5. Output Ripple and Noise – Si9113D1
Document Number: 71117
29-Feb-00
V_IN = 48 V
Outputs = At Full Load
Ch1 = 3.3 V (20 mV/div))
Ch3 = 40 V (100 mV/div)
FIGURE 6. Output Ripple and Noise – Si9113D2
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