SIC401A Datasheet, PDF (21/28 Pages) Vishay Siliconix – 15 A microBUCK SiC401A/B Integrated Buck Regulator with Programmable LDO

C_{OUT_min.} =
1 µH (10 +
1
2
x
4.43)²
(1.65)² - (1.5)²
C_{OUT_min.} = 316 µF
During the load release time, the voltage cross the inductor
is approximately - V_OUT. This causes a down-slope or falling
di/dt in the inductor. If the load dI/dt is not much faster than
the dI/dt of the inductor, then the inductor current will tend to
track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor; therefore a smaller capacitance can be used.
The following can be used to calculate the needed
capacitance for a given dI_LOAD/dt.
Peak inductor current is shown by the next equation.
I_LPK = I_max. + 1/2 x I_RIPPLEmax.
I_LPK = 10 + 1/2 x 4.43 = 12.215 A
Rate of change of load current = ^dILOAD
dt
I_max. = maximum load release = 15 A
Example
C_OUT
=
I_LPK
x
L
x
I_LPK
V_OUT
-
I_max.
dl_LOAD
x
2 (V_PK - V_OUT)
dt
dl_{LOAD =} 2.5 A
dt 1 µs
This would cause the output current to move from 15 A to
0 A in 4 µs, giving the minimum output capacitance
requirement shown in the following equation.
C_OUT = 12.215 x
1 µH x ^121..2515-
10
2.5
x
1
µs
2 (1.65 - 1.5)
C_OUT = 169 µF
Note that C_OUT is much smaller in this example, 169 µF
compared to 316 µF based on a worst case load release. To
meet the two design criteria of minimum 316 µF and
maximum 10.2 m ESR, select one capacitor of 330 µF and
9 m ESR.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the FB
input or because the FB ripple voltage is too low. This causes
the FB comparator to trigger prematurely after the 250 ns
minimum off-time has expired. In extreme cases the noise
can cause three or more successive on-times. Double-
pulsing will result in higher ripple voltage at the output, but in
SiC401A, SiC401BCD
Vishay Siliconix
most applications it will not affect operation. This form of
instability can usually be avoided by providing the FB pin with
a smooth, clean ripple signal that is at least 10 mVp-p, which
may dictate the need to increase the ESR of the output
capacitors. It is also imperative to provide a proper PCB
layout as discussed in the Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a small
(~ 10 pF) capacitor across the upper feedback resistor, as
shown in figure 13. This capacitor should be left unpopulated
until it can be confirmed that double-pulsing exists. Adding
the C_TOP capacitor will couple more ripple into FB to help
eliminate the problem. An optional connection on the PCB
should be available for this capacitor.
CTOP
VOUT
R1
R2
To FB pin
Figure 13 - Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking
stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and ringing.
Ringing for more than one cycle after the initial step is an
indication that the ESR should be increased.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10 mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other
is the ripple due to capacitive charging and discharging
during the switching cycle. For most applications the
minimum ESR ripple voltage is dominated by the output
capacitors, typically SP or POSCAP devices. For stability the
ESR zero of the output capacitor should be lower than
approximately one-third the switching frequency. The
formula for minimum ESR is shown by the following
equation.
3
ESR_min. = _{2 x π x COUT x fSW}
Document Number: 63835
For technical questions, contact: [e-mail]
www.vishay.com
S12-2109-Rev. C, 03-Sep-12
21
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000