Y162612K7560T9R Datasheet, PDF (2/4 Pages) Vishay Siliconix – Ultra High Precision Foil Wraparound Surface Mount Chip Resistor

VSMP Series (0805, 1206, 1506, 2010, 2512) (Z-Foil)
Vishay Foil Resistors
FIGURE 2 - TRIMMING TO VALUES
(Conceptual Illustration)
Interloop Capacitance
Reduction in Series
Mutual Inductance
Reduction due
to Change in
Current Direction
Current Path
Before Trimming
Current Path
After Trimming
Trimming Process
Removes this Material
from Shorting Strip Area
Changing Current Path
and Increasing
Resistance
Note: Foil shown in black, etched spaces in white
FIGURE 3 - TYPICAL RESISTANCE/
TEMPERATURE CURVE
+ 500
+ 400
+ 300
+ 200
ΔR ^{+ 100}
R
0
(ppm)- ₁₀₀
0.05 ppm/°C
- 200
- 300
- 400
- 500
- 0.1 ppm/°C
- 0.16 ppm/°C
0.1 ppm/°C
0.14 ppm/°C
0.2 ppm/°C
- 55 - 25 0 + 25 + 60 + 75 + 100 + 125
Ambient Temperature (°C) and TCR Chord Slopes for
Different Temperature Ranges
Note
• The TCR values for < 100 Ω are influenced by the termination
composition and result in deviation from this curve.
TABLE 2 - DIMENSIONS AND LAND PATTERN in Inches (Millimeters)
Top View
L
Recommended Land Pattern
T
D
CHIP
SIZE
L
W
± 0.005 (0.13) ± 0.005 (0.13)
0805
0.080 (2.03) 0.050 (1.27)
1206
0.126 (3.20) 0.062 (1.57)
1506
0.150 (3.81) 0.062 (1.57)
2010
0.198 (5.03) 0.097 (2.46)
2512
0.249 (6.32) 0.127 (3.23)
Note
(1) _{Land Pattern Dimensions are per IPC-7351A}
W
THICKNESS
MAXIMUM
0.025 (0.64)
0.025 (0.64)
0.025 (0.64)
0.025 (0.64)
0.025 (0.64)
X ^Footprint
G
Z
D
± 0.005 (0.13)
0.015 (0.38)
0.020 (0.51)
0.020 (0.51)
0.025 (0.64)
0.032 (0.81)
Z ⁽¹⁾
0.122 (3.10)
0.175 (4.45)
0.199 (5.05)
0.247 (6.27)
0.291 (7.39)
G ⁽¹⁾
0.028 (0.71)
0.059 (1.50)
0.083 (2.11)
0.115 (2.92)
0.150 (3.81)
X ⁽¹⁾
0.050 (1.27)
0.071 (1.80)
0.071 (1.80)
0.103 (2.62)
0.127 (3.23)
TABLE 3 - SPECIFICATIONS
CHIP
SIZE
RATED
POWER
(mW)
at + 70 °C
MAX.
WORKING
VOLTAGE
(≤ P × R )
RESISTANCE
RANGE
(Ω)
0805
200
1206
300
1506
300
2010
500
2512
750
40 V
87 V
95 V
187 V
220 V
10 to 8K
10 to 25K
10 to 30K
10 to 70K
10 to 125K
MAXIMUM
WEIGHT
(mg)
6
11
12
27
40
TABLE 4 - LOAD LIFE STABILITY
(+ 70 °C for 2000 h)
CHIP SIZE
MAXIMUM ΔR LIMITS
0805
± 0.005 % at 100 mW
± 0.01 % at 200 mW
1206, 1506
± 0.005 % at 150 mW
± 0.01 % at 300 mW
2010
± 0.005 % at 200 mW
± 0.01 % at 500 mW
2512
± 0.005 % at 500 mW
± 0.01 % at 750 mW
TABLE 5 - PERFORMANCES
TEST OR CONDITIONS
MIL-PRF-55342
CHARACTERISTIC E ΔR LIMITS
Thermal Shock, 100 x (- 65 °C to + 150 °C)
± 0.1 %
Low Temperature Operation, - 65 °C, 45 min at P_nom
Short Time Overload, 6.25 x Rated Power, 5 s
± 0.1 %
± 0.1 %
High Temperature Exposure, + 150 °C, 100 h
± 0.1 %
Resistance to Soldering Heat
± 0.2 %
Moisture Resistance
± 0.2 %
Load Life Stability + 70 °C for 2000 h at Rated Power
± 0.5 %
Note
(1) _{As shown + 0.01 Ω to allow for measurement errors at low values.}
TYPICAL
ΔR LIMITS
± 0.005 % (50 ppm)
± 0.005 % (50 ppm)
± 0.005 % (50 ppm)
± 0.01 % (100 ppm)
± 0.005 % (50 ppm)
± 0.005 % (50 ppm)
± 0.005 % (50 ppm)
MAXIMUM
ΔR LIMITS ⁽¹⁾
± 0.01 % (100 ppm)
± 0.01 % (100 ppm)
± 0.01 % (100 ppm)
± 0.02 % (200 ppm)
± 0.01 % (100 ppm)
± 0.02 % (200 ppm)
± 0.01 % (100 ppm)
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Document Number: 63060
Revision: 24-Mar-09