SIC632 Datasheet, PDF (2/19 Pages) Vishay Siliconix – 50 A VRPower Integrated Power Stage

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PINOUT CONFIGURATION
SiC632, SiC632A
Vishay Siliconix
PWM 1
ZCD_EN# 2
V_CIN 3
C_GND 4
BOOT 5
N.C. 6
PHASE 7
V_IN 8
31 30 29 28 27 26 25 24
GL
CGND
PGND
VIN
9 10 11 12 13 14 15
23 V_SWH
22 V_SWH
21 V_SWH
20 V_SWH
19 V_SWH
18 V_SWH
17 V_SWH
16 V_SWH
33
GL
V_SWH 23
V_SWH 22
V_SWH 21
V_SWH 20
V_SWH 19
V_SWH 18
V_SWH 17
V_SWH 16
24 25 26 27 28 29 30 31
GL
35
P_GND
32
C_GND
34
V_IN
15 14 13 12 11 10 9
1 PWM
2 ZCD_EN#
3 V_CIN
4 C_GND
5 ^BOOT
6 N.C.
7 PHASE
8 V_IN
Top view
Bottom view
Fig. 2 - SiC632 and SiC632A Pin Configuration
PIN CONFIGURATION
PIN NUMBER
NAME
1
PWM
2
ZCD_EN#
3
4, 32
5
6
7
8 to 11, 34
12 to 15, 28, 35
16 to 26
27, 33
29
30
31
V_CIN
C_GND
BOOT
N.C.
PHASE
V_IN
P_GND
V_SWH
GL
V_DRV
THWn
DSBL#
FUNCTION
PWM input logic
The ZCD_EN# pin enables or disables diode emulation. When ZCD_EN# is LOW, diode emulation is
allowed. When ZCD_EN# is HIGH, continuous conduction mode is forced.
ZCD_EN# can also be put in a high impedance mode by floating the pin. If both ZCD_EN# and PWM
are floating, the device shuts down and consumes typically 10 μA current.
Supply voltage for internal logic circuitry
Signal ground
High-side driver bootstrap voltage
Not connected internally, can be left floating or connected to ground
Return path of high-side gate driver
Power stage input voltage. Drain of high-side MOSFET
Power ground
Phase node of the power stage
Low-side MOSFET gate signal
Supply voltage for internal gate driver
Thermal warning open drain output
Disable pin. Active low
ORDERING INFORMATION
PART NUMBER
PACKAGE
SiC632CD-T1-GE3
PowerPAK MLP55-31L
SiC632ACD-T1-GE3
PowerPAK MLP55-31L
SiC632DB / SiC632ADB
MARKING CODE
SiC632
SiC632A
Reference board
OPTION
5 V PWM optimized
3.3 V PWM optimized
S15-2801-Rev. A, 30-Nov-15
2
Document Number: 62992
For technical questions, contact: [e-mail]
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000