DG2301 Datasheet, PDF (2/4 Pages) Vishay Siliconix – Minimal Propagation Delay Through The Switch

DG2301
Vishay Siliconix
New Product
ABSOLUTE MAXIMUM RATINGS
Reference to GND
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 V
OE, A, B^a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+ + 0.3 V)
Continuous Current (Any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . "50 mA
Peak Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "200 mA
(Pulsed at 1 ms, 10% duty cycle)
Storage Temperature (D Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Power Dissipation (Packages)^b
6-Pin SC70^c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mW
Notes:
a. Signals on A, or B or OE exceeding V+ will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC Board.
c. Derate 3.1 mW/_C above 70_C
SPECIFICATIONS (V+ = 5.0 V)
Parameter
DC Characteristics
Symbol
Test Conditions
Otherwise Unless Specified
V+ = 4.0 V to 5.5 V, V_OE = 0.8 or 2.0 V^e
Temp^a
Limits
-40 to 85_C
Min^b Typ^c Max^b
Unit
On-Resistance
r_ON
Switch Off Leakage Current
Switchl-On Leakage Current
Input High Voltage
Input Low Voltage
Input Current
I_(off)
I_(on)
V_IH
V_IL
I_IL or I_IH
Dynamic Characteristics
V+ = 4.5 V, V_A = 0 V, I_B = 64 mA
V+ = 4.5 V, V_A = 0 V, I_B = 30 mA
V+ = 4.5 V, V_A = 2.4 V, I_B = 15 mA
V+ = 4.0 V, V_A = 2.4 V, I_B = 15 mA
V+ = 5.5 V, V_A = 1 V/4.5 V, V_B = 4.5 V/1 V
V+ = 5.5 V, V_A = V_B = 1 V/4.5 V
V_OE = 0 or V+
Full
Full
Full
Full
Full
- 10
Full
- 10
Full
2.0
Full
Full
-1
7
7
W
15
20
10
mA
10
V
0.8
1
mA
Prop Delay Bus-to-Bus^f
Output Enable Time^d
Output Disable Time^d
Input Capacitance
Channel-Off Capacitance^d
Channel-On Capacitance^d
Power Supply
t_PHL
t_PLH
t_PZL
t_PZH
t_PLZ
t_PHZ
C_in
C_(off)
C_ON
V_LD = Open (Figure 1 and 2)
V_LD = 7 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
V_LD = 7 V, V+ = 4.0 V (Figure 1 and 2)
V_LD = Open, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
V_LD = Open, V+ = 4.0 V (Figure 1 and 2)
V_LD = 7 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
V_LD = 7 V, V+ = 4.0 V (Figure 1 and 2)
V_LD = Open, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
V_LD = Open, V+ = 4.0 V (Figure 1 and 2)
V_OE = 0 or V+, f = 1 MHz
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Room
Room
Room
1
1
3.9
4.5
3.7
ns
4.5
4.0
4.2
1.0
1.0
3.5
5
pF
11
Power Supply Range
V+
Power Supply Current
I+
V_OE = 0 or V+
4.0
5.5
V
0.01
1.0
mA
Notes:
a. Room = 25°C, Full = as determined by the operating suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for design aid only, not guaranteed nor subject to production testing.
d. Guarantee by design, nor subjected to production test.
e. V_IN = input voltage to perform proper function.
f. Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the on-resistance and
the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch.
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Document Number: 72049
S-03420—Rev. A, 03-Mar-03