SIC403_12 Datasheet, PDF (14/26 Pages) Vishay Siliconix – microBUCK SiC403 6 A, 28 V Integrated Buck Regulator with Programmable LDO

SiC403
Vishay Siliconix
V_DD
R_LDO1
R_LDO2
to FBL pin
Figure 9 - LDO Voltage Divider
The LDO output voltage is set by the following equation.
( ) ^{VLDO = 750 mV x}
1 + ^RLDO1
R_LDO2
A minimum 0.1 µF capacitor referenced to A_GND is equired
along with a minimum 1 µF capacitor referenced to P_GND to
filter the gate drive pulses. Refer to the layout guidelines
section for component placement suggestions.
.
LDO ENL Functions
The ENL input is used to control the internal LDO. When ENL
is low (grounded), the LDO is off. When ENL is above the V_IN
UVLO threshold, the LDO is enabled and the switcher is also
enabled if EN/PSV and V_DD meet the thresholds.
The ENL pin also acts as the switcher UVLO (undervoltage
lockout) for the V_IN supply. The V_IN UVLO voltage is
programmable via a resistor divider at the V_IN, ENL and
A_GND pins.
If the ENL pin transitions from high to low within 2 switching
cycles and is less than 1 V, then the LDO will turn off but the
switcher remains on. If the ENL goes below the V_IN UVLO
threshold and stays above 1 V, then the switcher will turn off
but the LDO remains on. The V_IN UVLO function has a typical
threshold of 2.6 V on the V_IN rising edge. The falling edge
threshold is 2.4 V.
Note that it is possible to operate the switcher with the LDO
disabled, but the ENL pin must be below the logic low
threshold (0.4 V max.). In this case, the UVLO function for
the input voltage cannot be used. The table below
summarizes the function of the ENL and EN pins, with
respect to the rising edge of ENL.
Figure 10 - ENL Threshold
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
• ENL pin
• V_IN input voltage
When the ENL pin is high and V_IN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when the
V_DD voltage (which is the LDO output voltage) is less than
0.75 V, the LDO initiates a current-limited start-up (typically
65 mA) to charge the output capacitors while protecting from
a short circuit event. When V_DD is greater than 0.75 V but still
less than 90 % of its final value (as sensed at the FBL pin),
the LDO current limit is increased to ~ 115mA. When V_DD
has reached 90 % of the final value (as sensed at the FBL
pin), the LDO current limit is increased to ~ 200 mA and the
LDO output is quickly driven to the nominal value by the
internal LDO regulator. It is recommended that during LDO
start-up to hold the PWM switching off until the LDO has
reached 90 % of the final value. This prevents overloading
the current-limited LDO output during the LDO start-up.
Due to the initial current limitations on the LDO during power
up (figure 11), any external load attached to the V_DD pin must
be limited to 20 mA before the LDO has reached 90 % of it
final regulation value.
EN
Low
High
Low
High
Low
High
ENL
Low, < 0.4 V
Low, < 0.4 V
High, < 2.6 V
High, < 2.6 V
High, > 2.6 V
High, > 2.6 V
LDO
Status
Off
Off
On
On
On
On
Switcher
Status
Off
On
Off
Off
Off
On
Figure 10 shows the ENL voltage thresholds and their effect
on LDO and switcher operation.
Figure 11 - LDO Start-Up
LDO Switchover Function
The SiC403 includes a switch-over function for the LDO. The
switch-over function is designed to increase efficiency by
using the more efficient DC/DC converter to power the LDO
output, avoiding the less efficient LDO regulator when
possible. The switch-over function connects the V_LDO pin
directly to the V_OUT pin using an internal switch. When the
switch-over is complete the LDO is turned off, which results
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Document Number: 66550
14
S12-0628-Rev. C, 19-Mar-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000