SIC402A Datasheet, PDF (14/26 Pages) Vishay Siliconix – 10 A microBUCK SiC402A/B Integrated Buck Regulator with Programmable LDO

SiC402A, SiC402BCD
Vishay Siliconix
SmartDrive^TM
For each DH pulse the DH driver initially turns on the high
side MOSFET at a lower speed, allowing a softer, smooth
turn-off of the low-side diode. Once the diode is off and the
LX voltage has risen 0.5 V above P_GND, the SmartDrive
circuit automatically drives the high-side MOSFET on at a
rapid rate. This technique reduces switching losses while
maintaining high efficiency and also avoids the need for
snubbers for the power MOSFETs.
Current Limit Protection
The device features programmable current limiting, which is
accomplished by using the R_DS(on) of the lower MOSFET for
current sensing. The current limit is set by R_ILIM resistor. The
R_ILIM resistor connects from the I_LIM pin to the LXS pin which
is also the drain of the low-side MOSFET. When the low-side
MOSFET is on, an internal ~ 10 µA current flows from the
I_LIM pin and through the R_ILIM resistor, creating a voltage
drop across the resistor. While the low-side MOSFET is on,
the inductor current flows through it and creates a voltage
across the R_DS(on). The voltage across the MOSFET is
negative with respect to ground. If this MOSFET voltage drop
exceeds the voltage across R_ILIM, the voltage at the I_LIM pin
will be negative and current limit will activate. The current
limit then keeps the low-side MOSFET on and will not allow
another high-side on-time, until the current in the low-side
MOSFET reduces enough to bring the I_LIM voltage back up
to zero. This method regulates the inductor valley current at
the level shown by I_LIM in figure 30.
IPEAK
ILOAD
ILIM
Soft-Start of PWM Regulator
SiC402A/B has a programmable soft-start time that is
controlled by an external capacitor at the SS pin. After the
controller meets both UVLO and EN/PSV thresholds, the
controller has an internal current source of 3 µA flowing
through the SS pin to charge the capacitor. During the start
up process (figure 31), 50 % of the voltage at the SS pin is
used as the reference for the FB comparator. The PWM
comparator issues an on-time pulse when the voltage at the
FB pin is less than 40 % of the SS pin. As a result, the output
voltage follows the SS voltage. The output voltage reaches
and maintains regulation when the soft start voltage is
 1.5 V. The time between the first LX pulse and V_OUT
reaching regulation is the soft-start time (t_SS). The
calculation for the soft-start time is shown by the following
equation.
t_SS
=
C_SS
x
1.5 V
3 μA
The voltage at the SS pin continues to ramp up and
eventually equals 64 % of V_DD. After the soft start completes,
the FB pin voltage is compared to an internal reference of
0.6 V. The delay time between the V_OUT regulation point and
P_GOOD going high is shown by the following equation.
t_PGOOD-DELAY =
C_SS x (0.64 x V_DD - 1.5 V)
3 μA
Figure 30 - Valley Current Limit
Setting the valley current limit to 10 A results in a peak
inductor current of 10 A plus peak ripple current. In this
situation, the average (load) current through the inductor is
10 A plus one-half the peak-to-peak ripple current.
The internal 10 µA current source is temperature
compensated at 4100 ppm in order to provide tracking with
the R_DS(on).
The R_ILIM value is calculated by the following equation.
R_ILIM = 446 x I_LIM x [0.099 x (5 V - V_DD) + 1]
When selecting a value for R_ILIM be sure not to exceed the
absolute maximum voltage value for the I_LIM pin. Note that
because the low-side MOSFET with low R_DS(on) is used for
current sensing, the PCB layout, solder connections, and
PCB connection to the LX node must be done carefully to
obtain good results. R_ILIM should be connected directly to
LXS (pin 28).
Figure 31 - Soft-Start Timing Diagram
Pre-Bias Startup
The SiC402A/B can start up normally even when there is an
existing output voltage present. The soft start time is still the
same as normal start up (when the output voltage starts from
zero). The output voltage starts to ramp up when 40 % of the
voltage at SS pin meets the existing FB voltage level.
Pre-bias startup is achieved by turning off the lower gate
when the inductor current falls below zero. This method
prevents the output voltage from discharging.
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Document Number: 63729
14
S12-2109-Rev. B, 03-Sep-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000