SI9135_11 Datasheet, PDF (13/16 Pages) Vishay Siliconix – SMBus Multi-Output Power-Supply Controller

DESCRIPTION OF OPERATION (CONT’D)
Buck Converter Operation
The 3.3 V and 5 V buck converters are both current-mode
PWM and PSM (during light load operation) regulators using
high-side bootstrap N-Channel and low-side N-Channel
MOSFETs. At light load conditions, the converters switch at
a lower frequency than the clock frequency, seen like some
clock pulses between the actual switching are skipped, this
operating condition is defined as pulse-skipping. The
operation of the converter(s) switching at clock frequency is
defined as normal operation.
Normal Operation: Buck Converters
In normal operation, the buck converter high-side MOSFET
is turned on with a delay (known as break-before-make time
- t_BBM), after the rising edge of the clock. After a certain on
time, the high-side MOSFET is turned off and then after a
delay (t_BBM), the low-side MOSFET is turned on until the next
rising edge of the clock, or the inductor current reaches zero.
The t_BBM (approximately 25 ns to 60 ns), has been optimized
to guarantee the efficiency is not adversely affected at the
high switching frequency and a specified minimum to
account for variations of possible MOSFET gate
capacitances.
During the normal operation, the high-side MOSFET switch
on-time is controlled internally to provide excellent line and
load regulation over temperature. Both buck converters
should have load, line, regulation to within 0.5 % tolerance.
Pulse Skipping: Buck Converters
When the buck converter switching frequency is less than
the internal clock frequency, its operation mode is defined as
pulse skipping mode. During this mode, the high-side
MOSFET is turned on until V_CS - V_FB reaches 20 mV, or the
on time reaches its maximum duty ratio. After the high-side
MOSFET is turned off, the low-side MOSFET is turned on
after the t_BBM delay, which will remain on until the inductor
current reaches zero. The output voltage will rise slightly
above the regulation voltage after this sequence, causing the
controller to stay idle for the next one, or several clock cycles.
When the output voltage falls slightly below the regulation
level, the high-side MOSFET will be turned on again at the
next clock cycle. With the converter remaining idle during
some clock cycles, the switching losses are reduced in order
to preserve conversion efficiency during the light output
current condition.
Si9135
Vishay Siliconix
Current Limit: Buck Converters
When the buck converter inductor current is too high, the
voltage across pin CS3(5) and pin FB3(5) exceeds
approximately 120 mV, the high-side MOSFET would be
turned off instantaneously regardless of the input, or output
condition. The Si9135 features clock cycle by clock cycle
current limiting capability.
Flyback Converter Operation
Designed mainly for PCMCIA or EEPROM programming, the
Si9135 has a 12 V output non-isolated buck boost converter,
called for brevity a flyback. It consists of two N-Channel
MOSFET switches that are turned on and off in phase, and
two diodes. Similar to the buck converter, during the light
load conditions, the flyback converter will switch at a
frequency lower than the internal clock frequency, which can
be defined as pulse skipping mode (PSM); otherwise, it is
operating in normal PWM mode.
Normal Operation: Flyback Converter
In normal operation mode, the two MOSFETs are turned on
at the rising edge of the clock, and then turned off. The on
time is controlled internally to provide excellent load, line,
and temperature regulation. The flyback converter has load,
line and temperature regulation well within 0.5 %.
Pulse Skipping: Flyback Converter
Under the light load conditions, similar to the buck converter,
the flyback converter will enter pulse skipping mode. The
MOSFETs will be turned on until the inductor current
increases to such a level that the voltage across the pin CSP
and pin CSN reaches 100 mV, or the on time reaches the
maximum duty cycle. After the MOSFETs are turned off, the
inductor current will conduct through two diodes until it
reaches zero. At this point, the flyback converter output will
rise slightly above the regulation level, and the converter will
stay idle for one or several clock cycle(s) until the output falls
back slightly below the regulation level. The switching losses
are reduced by skipping pulses and so the efficiency during
light load is preserved.
Current Limit: Flyback Converter
Similar to the buck converter; when the voltage across pin
CSP and pin CSN exceeds 410 mV typical, the two
MOSFETs will be turned off regardless of the input and
output conditions.
Document Number: 70817
www.vishay.com
S11-0975-Rev. D, 16-May-11
13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000